From patchwork Wed Nov 25 21:56:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bogicevic Sasa X-Patchwork-Id: 7703181 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 74203BF90C for ; Wed, 25 Nov 2015 21:56:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8C8A8208D0 for ; Wed, 25 Nov 2015 21:56:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4FEB208CD for ; Wed, 25 Nov 2015 21:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751966AbbKYV4k (ORCPT ); Wed, 25 Nov 2015 16:56:40 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:33714 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751703AbbKYV4j (ORCPT ); Wed, 25 Nov 2015 16:56:39 -0500 Received: by wmec201 with SMTP id c201so5694084wme.0; Wed, 25 Nov 2015 13:56:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=hvI72tTyhEZ8tUr+OftRc3YNFVR42az6K6moGbe9Yoc=; b=tv6E64iIJtGTadteNZnx8XMAiu5e8c/YdBbmDbhxc6GYH2z78MtI4T6d/fmn1/f+Yn wSej5RLh15xgjQTl2V+VSGPNn9lpxU7k8dk5mpShLAnH87Y9OG5IMfw/8PGKsNokEM5z 2XRwxS876NlFpWdepYSq0ZV4IUBUEPFuZZZ40hff8hs1KNbdIQ10qfSy60PTX3GmfMcY JbIP6KUWWC6oPkPetOExvmfTdJjOXnuJbjVEWzkzAIiLmTG90vLsvVoQ6ex+G9HTSGYN jLzhtsz5JlMMgddg4V44VR0nyimWnZiVtO4fm3WC7ZOaqDzu/AVMQJwjN4Nvp4gPKvEN 4ZUQ== X-Received: by 10.28.16.72 with SMTP id 69mr7505196wmq.100.1448488597739; Wed, 25 Nov 2015 13:56:37 -0800 (PST) Received: from localhost.localdomain (cable-24-135-16-197.dynamic.sbb.rs. [24.135.16.197]) by smtp.gmail.com with ESMTPSA id t2sm10075880wmt.1.2015.11.25.13.56.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Nov 2015 13:56:36 -0800 (PST) From: Bogicevic Sasa To: sudipm.mukherjee@gmail.com Cc: teddy.wang@siliconmotion.com, gregkh@linuxfoundation.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, Bogicevic Sasa Subject: [PATCH] drivers:staging:sm750fb Fix all space preferred around messages Date: Wed, 25 Nov 2015 22:56:30 +0100 Message-Id: <1448488590-1533-1-git-send-email-brutallesale@gmail.com> X-Mailer: git-send-email 2.1.4 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This fixes all messages from checkpatch.pl about space preferred Signed-off-by: Bogicevic Sasa --- drivers/staging/sm750fb/ddk750_mode.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index fa35926..0fd34fa 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -30,8 +30,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, | FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, LEFT, 0)); POKE32(CRT_AUTO_CENTERING_BR, - FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y-1) - | FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x-1)); + FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y - 1) + | FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x - 1)); /* Assume common fields in dispControl have been properly set before calling this function. @@ -101,9 +101,9 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); - ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| - FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE)| + ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity) | + FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity) | + FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE) | FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE); @@ -116,7 +116,7 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE); - POKE32(CRT_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(CRT_DISPLAY_CTRL, ulTmpValue | ulReg); } } else if (pll->clockType == PRIMARY_PLL) { @@ -140,15 +140,15 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); - ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| - FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| - FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)| - FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)| + ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity) | + FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity) | + FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity) | + FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE); ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)| + FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW); ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) @@ -167,13 +167,13 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) * next vertical sync to turn on/off the plane. */ - POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, ulTmpValue | ulReg); - while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) { + while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue | ulReg)) { cnt++; if (cnt > 1000) break; - POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); + POKE32(PANEL_DISPLAY_CTRL, ulTmpValue | ulReg); } } else { ret = -1;