From patchwork Sun Jun 12 13:30:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rithvik Patibandla X-Patchwork-Id: 9171505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9BCB56044F for ; Sun, 12 Jun 2016 13:30:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8950B24151 for ; Sun, 12 Jun 2016 13:30:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C67D26861; Sun, 12 Jun 2016 13:30:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDC8424151 for ; Sun, 12 Jun 2016 13:30:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753367AbcFLNas (ORCPT ); Sun, 12 Jun 2016 09:30:48 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34781 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753357AbcFLNar (ORCPT ); Sun, 12 Jun 2016 09:30:47 -0400 Received: by mail-pf0-f195.google.com with SMTP id 66so6807339pfy.1; Sun, 12 Jun 2016 06:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:mime-version:content-disposition :user-agent; bh=sc6s2+QaEyygNidviV/T+bCTAgZ/dv/D2DuVVy4iHNs=; b=w980UCoFpoG40kizv+KnhnQy25LTJPUX6Dm9RjKUVgSQ0YlOK/Zwa93Cn/siYkf5Ms 0zdSft0CkqHzCajUHO/mapKpDZguGUBDwhatd5zThw3V9mN1ICEQKBOiCB4j08SsWagO 7kcvRmAXKTz0UzzwCxW3OQYfiXGOIGSzUYApJ8y4s9KQ+K3l16d8wCMzd91eUce+82fQ hvuTb+hGyv1qXvx/qDWPyjXSaFgEpTWLHR2uP1wsAxyIpVV1fTN8JcU01nv6eGbi+wOV Xu3dbGGFBCbKO4K9ZBpx/Hzd25Xdi9dPnrOOb2pHqs6hViFbc4TRfK3nRGXe52k3qWZW 7Xjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=sc6s2+QaEyygNidviV/T+bCTAgZ/dv/D2DuVVy4iHNs=; b=VX1iJFJvY0IxAZnZXRXkh3mZXr3YZd7zYafu2sgf0BKjpxdACrKYHPGMVLsAvI//se mP8P9rCqhhIg84yFVvrE1RqCky4u3ZjnHeCBOZZ8c/9B8IInmO1EKUT7MJBKOpOmXuLO EOgSlK0Bv1iVVAx32NYoL1z5HZ9t0LbLVRVU1YQNw8DuibGhBrLmReGSRhFWj8KlRFTJ jX7S59IgUo1YkwaWj2zN1GG85+GI3VsxlcWGFwMlntdVgDCZe9Uf5UuJ7IVrsUDPKMui A0U70UVXpDDAvOrhb8CY97Pbi6UWk7TGPpliSZ1OwvTBcJ+mFBF7RAUz/KlsfHn6/+Qo W9Mg== X-Gm-Message-State: ALyK8tJzVKBmhdxpHg2UQzjcQ6ae6gybh+5NB8Hr9x4oEu7psj5z24+OKSopt8DCNORBcg== X-Received: by 10.98.48.198 with SMTP id w189mr12256474pfw.125.1465738246142; Sun, 12 Jun 2016 06:30:46 -0700 (PDT) Received: from localhost ([125.17.242.34]) by smtp.gmail.com with ESMTPSA id u65sm30577893pfa.9.2016.06.12.06.30.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Jun 2016 06:30:45 -0700 (PDT) Date: Sun, 12 Jun 2016 19:00:41 +0530 From: Rithvik Patibandla To: sudipm.mukherjee@gmail.com Cc: teddy.wang@siliconmotion.com, gregkh@linuxfoundation.org, linux-fbdev@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH] Staging:sm750fb:ddk750_chip.c:Fixed coding style in comments Message-ID: <20160612133041.GA3709@rithvik-IdeaPad> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The following patch fixes format of some comments. Signed-off-by: Rithvik Patibandla --- drivers/staging/sm750fb/ddk750_chip.c | 71 +++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 33 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index f80ee77..8cb5cb9 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -70,11 +70,11 @@ static void setChipClock(unsigned int frequency) pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ pll.clockType = MXCLK_PLL; - /* - * Call calcPllValue() to fill up the other fields for PLL structure. - * Sometime, the chip cannot set up the exact clock required by User. - * Return value from calcPllValue() gives the actual possible clock. - */ + /* + * Call calcPllValue() to fill up the other fields for PLL structure. + * Sometime, the chip cannot set up the exact clock required by User. + * Return value from calcPllValue() gives the actual possible clock. + */ ulActualMxClk = calcPllValue(frequency, &pll); /* Master Clock Control: MXCLK_PLL */ @@ -86,13 +86,15 @@ static void setMemoryClock(unsigned int frequency) { unsigned int reg, divisor; - /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ +/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) return; if (frequency) { - /* Set the frequency to the maximum frequency that the DDR Memory can take - which is 336MHz. */ + /* + * Set the frequency to the maximum frequency that the DDR Memory can + * take which is 336MHz. + */ if (frequency > MHz(336)) frequency = MHz(336); @@ -133,13 +135,15 @@ static void setMasterClock(unsigned int frequency) { unsigned int reg, divisor; - /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ +/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) return; if (frequency) { - /* Set the frequency to the maximum frequency that the SM750 engine can - run, which is about 190 MHz. */ + /* + * Set the frequency to the maximum frequency that the SM750 engine can + * run, which is about 190 MHz. + */ if (frequency > MHz(190)) frequency = MHz(190); @@ -236,9 +240,10 @@ int ddk750_initHw(initchip_param_t *pInitParam) setMasterClock(MHz(pInitParam->masterClock)); - /* Reset the memory controller. If the memory controller is not reset in SM750, - the system might hang when sw accesses the memory. - The memory should be resetted after changing the MXCLK. + /* + * Reset the memory controller. If the memory controller is not reset + * in SM750, the system might hang when sw accesses the memory.The + * memory should be resetted after changing the MXCLK. */ if (pInitParam->resetMemory == 1) { reg = PEEK32(MISC_CTRL); @@ -282,24 +287,23 @@ int ddk750_initHw(initchip_param_t *pInitParam) } /* - monk liu @ 4/6/2011: - re-write the calculatePLL function of ddk750. - the original version function does not use some mathematics tricks and shortcut - when it doing the calculation of the best N,M,D combination - I think this version gives a little upgrade in speed - - 750 pll clock formular: - Request Clock = (Input Clock * M )/(N * X) - - Input Clock = 14318181 hz - X = 2 power D - D ={0,1,2,3,4,5,6} - M = {1,...,255} - N = {2,...,15} -*/ + * monk liu @ 4/6/2011: + * re-write the calculatePLL function of ddk750. the original version + * function does not use some mathematics tricks and shortcut when it + * doing the calculation of the best N,M,D combination. I think this + * version gives a little upgrade in speed + * + * 750 pll clock formular: +* Request Clock = (Input Clock * M )/(N * X) + * Input Clock = 14318181 hz + * X = 2 power D + * D ={0,1,2,3,4,5,6} + * M = {1,...,255} + * N = {2,...,15} + */ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) { - /* as sm750 register definition, N located in 2,15 and M located in 1,255 */ +/* as sm750 register definition, N located in 2,15 and M located in 1,255 */ int N, M, X, d; int mini_diff; unsigned int RN, quo, rem, fl_quo; @@ -310,7 +314,8 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) if (getChipType() == SM750LE) { /* SM750LE don't have prgrammable PLL and M/N values to work on. - Just return the requested clock. */ + * Just return the requested clock. + */ return request_orig; } @@ -319,12 +324,12 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) request = request_orig / 1000; input = pll->inputFreq / 1000; - /* for MXCLK register , no POD provided, so need be treated differently */ +/* for MXCLK register , no POD provided, so need be treated differently */ if (pll->clockType == MXCLK_PLL) max_d = 3; for (N = 15; N > 1; N--) { - /* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ +/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ RN = N * request; quo = RN / input; rem = RN % input;/* rem always small than 14318181 */