From patchwork Tue Feb 7 02:35:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: cailiwei X-Patchwork-Id: 9559077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B1C6A60236 for ; Tue, 7 Feb 2017 02:37:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A44F02236A for ; Tue, 7 Feb 2017 02:37:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9749927FA8; Tue, 7 Feb 2017 02:37:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A61152236A for ; Tue, 7 Feb 2017 02:37:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751789AbdBGChJ (ORCPT ); Mon, 6 Feb 2017 21:37:09 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:19388 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751618AbdBGChI (ORCPT ); Mon, 6 Feb 2017 21:37:08 -0500 Received: from 172.24.1.136 (EHLO szxeml433-hub.china.huawei.com) ([172.24.1.136]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DUE66725; Tue, 07 Feb 2017 10:37:00 +0800 (CST) Received: from huawei.com (100.106.171.187) by szxeml433-hub.china.huawei.com (10.82.67.210) with Microsoft SMTP Server id 14.3.235.1; Tue, 7 Feb 2017 10:36:51 +0800 From: cailiwei To: , , , CC: , , , , , Subject: [PATCH 8/8] fb: hisilicon: Add framebuffer driver for hi3660 SoC Date: Tue, 7 Feb 2017 10:35:59 +0800 Message-ID: <20170207023559.79455-8-cailiwei@hisilicon.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170207023559.79455-1-cailiwei@hisilicon.com> References: <20170207023559.79455-1-cailiwei@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [100.106.171.187] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.589932CC.0206, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f4aba5a7c56aebc184502ba5ceda4896 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Levy-Cai Add framebuffer driver for hi3660 SoC, this driver include lcd driver & Hdmi adv7533/adv7535 driver, support lcd display at 1080p@60 and hdmi display at 1080p@60. Signed-off-by: cailiwei --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 48 +++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi old mode 100644 new mode 100755 index 5389799ff371..2ad11800dd67 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -132,6 +132,54 @@ clock-frequency = <1920000>; }; + /* display start */ + framebuffer@E8600000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "hisilicon,hisifb"; + fastboot_enable_flag = <0>; + fake_lcd_flag = <0>; + dss_base_phy = <0xE8600000>; + // DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, MMBUF_CFG + reg = <0 0xE8600000 0 0x80000>, <0 0xFFF35000 0 0x1000>, <0 0xFFF0A000 0 0x1000>, <0 0xE8A09000 0 0x1000>, + <0 0xE86C0000 0 0x10000>, <0 0xFFF02000 0 0x1000>, <0 0xFFF31000 0 0x1000>; + // dss-pdp, dss-sdp, dss-adp, dss-dsi0, dss-dsi1 irq + interrupts = <0 245 4>, <0 246 4>, <0 247 4>, <0 251 4>, <0 252 4>; + //regulator_dsssubsys-supply = <&dsssubsys>; + //regulator_mmbuf-supply = <&mmbuf>; + clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>, <&crg_ctrl HI3660_PCLK_GATE_DSS>, <&crg_ctrl HI3660_CLK_GATE_EDC0>, + <&crg_ctrl HI3660_CLK_GATE_LDI0>, <&crg_ctrl HI3660_CLK_GATE_LDI1>, <&sctrl HI3660_CLK_GATE_DSS_AXI_MM>, + <&sctrl HI3660_PCLK_GATE_MMBUF>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>, + <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>, <&crg_ctrl HI3660_PCLK_GATE_DSI0>, + <&crg_ctrl HI3660_PCLK_GATE_DSI1>;//, <&crg_ctrl HI3660_PCLK_GATE_PCTRL>; + clock-names = "aclk_dss", "pclk_dss", "clk_edc0", "clk_ldi0", "clk_ldi1", + "clk_dss_axi_mm", "pclk_mmbuf", + "clk_txdphy0_ref", "clk_txdphy1_ref", "clk_txdphy0_cfg", "clk_txdphy1_cfg", + "pclk_dsi0", "pclk_dsi1";//, "pclk_pctrl"; + status = "ok"; + fpga_flag = <0>; + + /*iommu_info { + start-addr = <0x8000>; + size = <0xbfff8000>; + };*/ + }; + + panel_lcd_hikey { + #address-cells = <2>; + #size-cells = <2>; + compatible = "hisilicon,mipi_hikey"; + lcd-bl-type = <0>; + lcd-display-type = <8>; + //vdd-supply = <&ldo3>; + lcd-ifbc-type = <0>; + gpios = <&gpio27 0 0>, <&gpio27 2 0>, <&gpio22 6 0>, <&gpio2 4 0>; + gpio_nums = <216 218 182 20>; + fpga_flag = <0>; + status = "disabled"; + }; + /* display end */ + soc { compatible = "simple-bus"; #address-cells = <2>;