From patchwork Fri Jun 30 11:21:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 9819309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 885C26035F for ; Fri, 30 Jun 2017 11:23:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73B4428576 for ; Fri, 30 Jun 2017 11:23:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68344285F1; Fri, 30 Jun 2017 11:23:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAFC928576 for ; Fri, 30 Jun 2017 11:23:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751638AbdF3LVu (ORCPT ); Fri, 30 Jun 2017 07:21:50 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:37428 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751584AbdF3LVX (ORCPT ); Fri, 30 Jun 2017 07:21:23 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 6237826BF71 From: Enric Balletbo i Serra To: Thierry Reding , Lee Jones , Daniel Thompson , Jingoo Han , Bartlomiej Zolnierkiewicz , Rob Herring , Pavel Machek , Richard Purdie , Jacek Anaszewski , Heiko Stuebner Cc: linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 3/4] ARM: dts: rockchip: set pre/post pwm-delay-us property. Date: Fri, 30 Jun 2017 13:21:08 +0200 Message-Id: <20170630112109.13785-3-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170630112109.13785-1-enric.balletbo@collabora.com> References: <20170630112109.13785-1-enric.balletbo@collabora.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For veyron the binding should provide both pwm timings, the delay between you enable the PWM and set the enable signal, and the delay between you disable the PWM signal and clear the enable signal. Update the binding accordingly, in this case the panels connected to the veyron boards have a symetric power sequence, hence the same value is used. Signed-off-by: Enric Balletbo i Serra --- Changes since v1: - Add this new patch to fix current binding on veyron. arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index d752a31..c0e8ce2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -96,7 +96,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwms = <&pwm0 0 1000000 0>; - pwm-delay-us = <10000>; + pwm-delay-us = <10000 10000>; }; gpio-charger {