From patchwork Fri Feb 16 17:40:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 10225257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DF7DA602CB for ; Fri, 16 Feb 2018 17:41:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCBF4286E4 for ; Fri, 16 Feb 2018 17:41:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C11172960A; Fri, 16 Feb 2018 17:41:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F33B286E4 for ; Fri, 16 Feb 2018 17:41:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752448AbeBPRlF (ORCPT ); Fri, 16 Feb 2018 12:41:05 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:34444 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1162328AbeBPRks (ORCPT ); Fri, 16 Feb 2018 12:40:48 -0500 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id B03EB271FEF From: Enric Balletbo i Serra To: Lee Jones , Daniel Thompson , Jingoo Han , Rob Herring , Pavel Machek , Heiko Stuebner Cc: Thierry Reding , Bartlomiej Zolnierkiewicz , Richard Purdie , Jacek Anaszewski , linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, groeck@chromium.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [RESEND PATCH v5 4/5] ARM: dts: rockchip: set PWM delay backlight settings for Veyron. Date: Fri, 16 Feb 2018 18:40:33 +0100 Message-Id: <20180216174034.15936-4-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180216174034.15936-1-enric.balletbo@collabora.com> References: <20180216174034.15936-1-enric.balletbo@collabora.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For veyron the binding should provide both PWM timings, the delay between you enable the PWM and set the enable signal, and the delay between you disable the PWM signal and clear the enable signal. Update the binding accordingly, in this case the panels connected to the veyron boards have a symmetric power sequence, hence the same value is used. Signed-off-by: Enric Balletbo i Serra Acked-by: Pavel Machek --- Changes since v4: - Rebased on top of mainline. Changes since v3: - Use new -ms names for proprieties. Changes since v2: - Use new names for proprieties. Changes since v1: - Add this new patch to fix current binding on veyron. arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index be487111d025..b16d570ff029 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -95,7 +95,8 @@ pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwms = <&pwm0 0 1000000 0>; - pwm-delay-us = <10000>; + post-pwm-on-delay-ms = <10>; + pwm-off-delay-ms = <10>; }; gpio-charger {