From patchwork Wed Mar 28 17:03:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 10313667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6AF2C60467 for ; Wed, 28 Mar 2018 17:04:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C4E2297BA for ; Wed, 28 Mar 2018 17:04:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 508D729F14; Wed, 28 Mar 2018 17:04:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE142297BA for ; Wed, 28 Mar 2018 17:04:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752447AbeC1REL (ORCPT ); Wed, 28 Mar 2018 13:04:11 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:48796 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752067AbeC1RDk (ORCPT ); Wed, 28 Mar 2018 13:03:40 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 7462C275F0B From: Enric Balletbo i Serra To: Lee Jones , Daniel Thompson , Jingoo Han , Rob Herring , Pavel Machek , Heiko Stuebner Cc: Thierry Reding , Bartlomiej Zolnierkiewicz , Richard Purdie , Jacek Anaszewski , linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, groeck@chromium.org, linux-rockchip@lists.infradead.org, linux-leds@vger.kernel.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [RESEND PATCH v6 4/5] ARM: dts: rockchip: set PWM delay backlight settings for Veyron. Date: Wed, 28 Mar 2018 19:03:26 +0200 Message-Id: <20180328170327.5395-4-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180328170327.5395-1-enric.balletbo@collabora.com> References: <20180328170327.5395-1-enric.balletbo@collabora.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For veyron the binding should provide both PWM timings, the delay between you enable the PWM and set the enable signal, and the delay between you disable the PWM signal and clear the enable signal. Update the binding accordingly, in this case the panels connected to the veyron boards have a symmetric power sequence, hence the same value is used. Signed-off-by: Enric Balletbo i Serra Acked-by: Pavel Machek --- Changes since v5: - None. Changes since v4: - Rebased on top of mainline. Changes since v3: - Use new -ms names for proprieties. Changes since v2: - Use new names for proprieties. Changes since v1: - Add this new patch to fix current binding on veyron. --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index d752a315f884..5a8c7f3abb38 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -96,7 +96,8 @@ pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwms = <&pwm0 0 1000000 0>; - pwm-delay-us = <10000>; + post-pwm-on-delay-ms = <10>; + pwm-off-delay-ms = <10>; }; gpio-charger {