From patchwork Wed Apr 7 06:36:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavle Rohalj X-Patchwork-Id: 12187081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CB9CC433B4 for ; Wed, 7 Apr 2021 06:36:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 278AE6124C for ; Wed, 7 Apr 2021 06:36:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348889AbhDGGgb (ORCPT ); Wed, 7 Apr 2021 02:36:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348885AbhDGGg0 (ORCPT ); Wed, 7 Apr 2021 02:36:26 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B73E6C06175F; Tue, 6 Apr 2021 23:36:17 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id a12so12180796pfc.7; Tue, 06 Apr 2021 23:36:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xEkX5xSjIsagQqqLDFxiiQocHiJ/DDzwHuOshMgpbFw=; b=thYSJ9fjJlSSwyX6GUt3rRzrmDkI7jRCiejyv36KZESRkC1Buo07GU2mBUv5Sl96xn mCaCArjZVQ4GZ4+K6PecXJ/uVQHJkTb2G/fKBtE7crWceT5U8qUteyMnO35xry4KXKoB Q8mLA10zpeGlXLG3PNNCoYQzzZrpse6K3tRnC/LeXgM3ttPNtjBfXvu8uNCLtcRcvXvX f3HBa39r6Y1kLQe6pHXhhnoiHcEf9eKbln7t1onx6DoXSQ/91S1utXQOqf60Jmv80MaK lSJKfx14qYkjsLDhlmuECsLwDmRMWZm/odkBTvW2GQLqoCXPiPw2bO0kkryf9xmVc/kv MQ8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xEkX5xSjIsagQqqLDFxiiQocHiJ/DDzwHuOshMgpbFw=; b=ZxdrRqaA98MtMUeHeoxucihb9YUrr0C6KxvjY9nAeo15gwRMuKQguzNSFWs0vwZosv WUK32xOdkcX+Lguz98h/EIMq12jXYvihxrtSdbjgiEc5HAws7YkhsmKIx173Atj+g1hZ WM5UxCf0i9j37w5Pr3NAto/d5OppSpHA6xYdd3rUh4wDNy2E8z2Va9vz2E0UN5aDBMZ4 Z8dnj0zgEjTAbzwFOfaj0cR8bSCyeHIRWIRcgkspN4BelK1v8yFe0gwDel4FJRjfCnko AAzhcxYQEaHS8XHW9CiACBAb+6fbKXMbXD75e1eeNEv8ufQLcN5L7jcoZsL4juUHpR2x nAsA== X-Gm-Message-State: AOAM532TkW7l4zwDbKnRKT9nNn9jv5/27/eTCjiXxXAKS8jBAtals078 tN7yWHW+Jv902QBtzjvjrm8= X-Google-Smtp-Source: ABdhPJzJX/CCjqvdgLevX1W2VlwM9ac6ztUBQ5HQwtFm9/0EtFQRMYZ5VJhD3cQGXHJpAPn/79vU9g== X-Received: by 2002:a05:6a00:2288:b029:202:2103:3f21 with SMTP id f8-20020a056a002288b029020221033f21mr1482523pfe.39.1617777377290; Tue, 06 Apr 2021 23:36:17 -0700 (PDT) Received: from localhost.localdomain ([134.173.248.5]) by smtp.gmail.com with ESMTPSA id w18sm4063739pjh.19.2021.04.06.23.36.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 23:36:16 -0700 (PDT) Date: Tue, 6 Apr 2021 23:36:14 -0700 From: Pavle Rohalj To: sudipm.mukherjee@gmail.com, teddy.wang@siliconmotion.com, gregkh@linuxfoundation.org, linux-fbdev@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/49] staging: sm750fb: Update programModeRegisters to snake case Message-ID: <6d74a0eb5c1b1dd21ece0520e2c96f1b83df15c8.1617776878.git.pavle.rohalj@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Fix "Avoid CamelCase" checkpatch.pl check for the function programModeRegisters, including its name, parameters, and body. Signed-off-by: Pavle Rohalj --- drivers/staging/sm750fb/ddk750_mode.c | 48 +++++++++++++-------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 2fae81b47f46..5c685b4e2fd6 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -75,7 +75,7 @@ display_control_adjust_sm750le(struct mode_parameter *mode_param, } /* only timing related registers will be programed */ -static int programModeRegisters(struct mode_parameter *pModeParam, +static int program_mode_registers(struct mode_parameter *mode_param, struct pll_value *pll) { int ret = 0; @@ -86,46 +86,46 @@ static int programModeRegisters(struct mode_parameter *pModeParam, /* programe secondary pixel clock */ poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); - tmp = ((pModeParam->horizontal_total - 1) << + tmp = ((mode_param->horizontal_total - 1) << CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & CRT_HORIZONTAL_TOTAL_TOTAL_MASK; - tmp |= (pModeParam->horizontal_display_end - 1) & + tmp |= (mode_param->horizontal_display_end - 1) & CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK; poke32(CRT_HORIZONTAL_TOTAL, tmp); - tmp = (pModeParam->horizontal_sync_width << + tmp = (mode_param->horizontal_sync_width << CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) & CRT_HORIZONTAL_SYNC_WIDTH_MASK; - tmp |= (pModeParam->horizontal_sync_start - 1) & + tmp |= (mode_param->horizontal_sync_start - 1) & CRT_HORIZONTAL_SYNC_START_MASK; poke32(CRT_HORIZONTAL_SYNC, tmp); - tmp = ((pModeParam->vertical_total - 1) << + tmp = ((mode_param->vertical_total - 1) << CRT_VERTICAL_TOTAL_TOTAL_SHIFT) & CRT_VERTICAL_TOTAL_TOTAL_MASK; - tmp |= (pModeParam->vertical_display_end - 1) & + tmp |= (mode_param->vertical_display_end - 1) & CRT_VERTICAL_TOTAL_DISPLAY_END_MASK; poke32(CRT_VERTICAL_TOTAL, tmp); - tmp = ((pModeParam->vertical_sync_height << + tmp = ((mode_param->vertical_sync_height << CRT_VERTICAL_SYNC_HEIGHT_SHIFT)) & CRT_VERTICAL_SYNC_HEIGHT_MASK; - tmp |= (pModeParam->vertical_sync_start - 1) & + tmp |= (mode_param->vertical_sync_start - 1) & CRT_VERTICAL_SYNC_START_MASK; poke32(CRT_VERTICAL_SYNC, tmp); tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; - if (pModeParam->vertical_sync_polarity) + if (mode_param->vertical_sync_polarity) tmp |= DISPLAY_CTRL_VSYNC_PHASE; - if (pModeParam->horizontal_sync_polarity) + if (mode_param->horizontal_sync_polarity) tmp |= DISPLAY_CTRL_HSYNC_PHASE; if (sm750_get_chip_type() == SM750LE) { - display_control_adjust_sm750le(pModeParam, tmp); + display_control_adjust_sm750le(mode_param, tmp); } else { reg = peek32(CRT_DISPLAY_CTRL) & ~(DISPLAY_CTRL_VSYNC_PHASE | @@ -140,40 +140,40 @@ static int programModeRegisters(struct mode_parameter *pModeParam, poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); - reg = ((pModeParam->horizontal_total - 1) << + reg = ((mode_param->horizontal_total - 1) << PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & PANEL_HORIZONTAL_TOTAL_TOTAL_MASK; - reg |= ((pModeParam->horizontal_display_end - 1) & + reg |= ((mode_param->horizontal_display_end - 1) & PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK); poke32(PANEL_HORIZONTAL_TOTAL, reg); poke32(PANEL_HORIZONTAL_SYNC, - ((pModeParam->horizontal_sync_width << + ((mode_param->horizontal_sync_width << PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) & PANEL_HORIZONTAL_SYNC_WIDTH_MASK) | - ((pModeParam->horizontal_sync_start - 1) & + ((mode_param->horizontal_sync_start - 1) & PANEL_HORIZONTAL_SYNC_START_MASK)); poke32(PANEL_VERTICAL_TOTAL, - (((pModeParam->vertical_total - 1) << + (((mode_param->vertical_total - 1) << PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) & PANEL_VERTICAL_TOTAL_TOTAL_MASK) | - ((pModeParam->vertical_display_end - 1) & + ((mode_param->vertical_display_end - 1) & PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK)); poke32(PANEL_VERTICAL_SYNC, - ((pModeParam->vertical_sync_height << + ((mode_param->vertical_sync_height << PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) & PANEL_VERTICAL_SYNC_HEIGHT_MASK) | - ((pModeParam->vertical_sync_start - 1) & + ((mode_param->vertical_sync_start - 1) & PANEL_VERTICAL_SYNC_START_MASK)); tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; - if (pModeParam->vertical_sync_polarity) + if (mode_param->vertical_sync_polarity) tmp |= DISPLAY_CTRL_VSYNC_PHASE; - if (pModeParam->horizontal_sync_polarity) + if (mode_param->horizontal_sync_polarity) tmp |= DISPLAY_CTRL_HSYNC_PHASE; - if (pModeParam->clock_phase_polarity) + if (mode_param->clock_phase_polarity) tmp |= DISPLAY_CTRL_CLOCK_PHASE; reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK | @@ -220,6 +220,6 @@ int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock) outb_p(0x88, 0x3d4); outb_p(0x06, 0x3d5); } - programModeRegisters(parm, &pll); + program_mode_registers(parm, &pll); return 0; }