From patchwork Thu Jun 26 19:20:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 4431011 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7C4CDBEEAA for ; Thu, 26 Jun 2014 19:21:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AF775202FF for ; Thu, 26 Jun 2014 19:21:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BC6F0202D1 for ; Thu, 26 Jun 2014 19:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751502AbaFZTVh (ORCPT ); Thu, 26 Jun 2014 15:21:37 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:48805 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbaFZTVf (ORCPT ); Thu, 26 Jun 2014 15:21:35 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5QJLHZ4030676; Thu, 26 Jun 2014 14:21:17 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5QJLGuK021812; Thu, 26 Jun 2014 14:21:17 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Thu, 26 Jun 2014 14:21:16 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5QJLFBg021486; Thu, 26 Jun 2014 14:21:16 -0500 From: Jyri Sarha To: , , CC: , , , , , , Jyri Sarha Subject: [PATCH 03/12] OMAPDSS: hdmi_wp: Add function for getting hdmi_wp physical base address Date: Thu, 26 Jun 2014 22:20:54 +0300 Message-ID: <71e703f319eacd5a7196d8b34601b52e32b946d3.1403807781.git.jsarha@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The hdmi_wp physical base address is needed for hdmi audio dma. Signed-off-by: Jyri Sarha --- drivers/video/fbdev/omap2/dss/hdmi.h | 2 ++ drivers/video/fbdev/omap2/dss/hdmi_wp.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index 1f01068..927cb4d 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h @@ -250,6 +250,7 @@ struct hdmi_core_audio_config { struct hdmi_wp_data { void __iomem *base; + phys_addr_t phys_base; }; struct hdmi_pll_data { @@ -317,6 +318,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, struct omap_video_timings *timings, struct hdmi_config *param); int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); +phys_addr_t hdmi_wp_get_phys_addr(struct hdmi_wp_data *wp); /* HDMI PLL funcs */ int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); diff --git a/drivers/video/fbdev/omap2/dss/hdmi_wp.c b/drivers/video/fbdev/omap2/dss/hdmi_wp.c index 496327e..eadd4ed 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_wp.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_wp.c @@ -247,6 +247,7 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) DSSERR("can't get WP mem resource\n"); return -EINVAL; } + wp->phys_base = res->start; wp->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(wp->base)) { @@ -256,3 +257,8 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) return 0; } + +phys_addr_t hdmi_wp_get_phys_addr(struct hdmi_wp_data *wp) +{ + return wp->phys_base; +}