From patchwork Mon Jun 3 10:13:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 2651801 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id D3132DF24C for ; Mon, 3 Jun 2013 10:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757119Ab3FCKOg (ORCPT ); Mon, 3 Jun 2013 06:14:36 -0400 Received: from mail-we0-f177.google.com ([74.125.82.177]:33145 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756810Ab3FCKNo (ORCPT ); Mon, 3 Jun 2013 06:13:44 -0400 Received: by mail-we0-f177.google.com with SMTP id m19so738514wev.22 for ; Mon, 03 Jun 2013 03:13:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:content-type:x-gm-message-state; bh=uHAeuAu4ZypyqoKDEUJYTzD49kSImhXRjwrTd/Nj+tQ=; b=aGowgFceSnRrYHZq+xQd1nqXhdnorUbcNmQ+2BS1peQvvbLEOa1SPFoNGDPkTW86+d bJN3Bui2HZFkEgaII0bT48GkvCscmS2F1ENPO1psfvnSl0uBzfyFCbI92OkBAy+rhtez L7SBrRl+Swu0R2TCyMVSgK90uh+7QlX2kQy59FG9YXGdVGztT00gU9ulyI61ndXBGOuL sWpfIYXiOouC0sAo94HZ0wcA5qQrTs29BWaM5xqDiK5/7gAYOuUJyhVDPS3LKa/ZkcDK ILpQ6nAgzl4pfsxISKWcm2ydKB803fh1f1vCfx6bE2QxMTxP/VZK4lRmtwjKSm7hWioh Fvww== X-Received: by 10.180.11.206 with SMTP id s14mr11678221wib.40.1370254423535; Mon, 03 Jun 2013 03:13:43 -0700 (PDT) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id m3sm22328365wij.5.2013.06.03.03.13.41 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 03 Jun 2013 03:13:42 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org Cc: Michal Simek , Michal Simek , Arnd Bergmann , Timur Tabi , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , linux-fbdev@vger.kernel.org Subject: [PATCH v4 6/7] video: xilinxfb: Add support for little endian accesses Date: Mon, 3 Jun 2013 12:13:21 +0200 Message-Id: <818df253e24e333befbbdb35c027a3cece1830a9.1370254386.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQnoui/gW+DdQOuMTQ1l/rbAP1AXTO+B8956xcuLUo9rRo2QN8WMVBIrver+zXpbXMcn2I9E Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Dynamically detect endianess on IP and use ioread/iowrite functions instead of powerpc and microblaze specific out_be32. Signed-off-by: Michal Simek Acked-by: Arnd Bergmann --- Changes in v4: - Acked by Arnd Changes in v3: - New patch in this patchset based on discussions Changes in v2: None drivers/video/xilinxfb.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) -- 1.8.2.3 diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index bd3b85d..f3d4a69 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -117,6 +117,7 @@ static struct fb_var_screeninfo xilinx_fb_var = { #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ +#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ struct xilinxfb_drvdata { @@ -153,14 +154,33 @@ struct xilinxfb_drvdata { static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, u32 val) { - if (drvdata->flags & BUS_ACCESS_FLAG) - out_be32(drvdata->regs + (offset << 2), val); + if (drvdata->flags & BUS_ACCESS_FLAG) { + if (drvdata->flags & LITTLE_ENDIAN_ACCESS) + iowrite32(val, drvdata->regs + (offset << 2)); + else + iowrite32be(val, drvdata->regs + (offset << 2)); + } #ifdef CONFIG_PPC_DCR else dcr_write(drvdata->dcr_host, offset, val); #endif } +static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset) +{ + if (drvdata->flags & BUS_ACCESS_FLAG) { + if (drvdata->flags & LITTLE_ENDIAN_ACCESS) + return ioread32(drvdata->regs + (offset << 2)); + else + return ioread32be(drvdata->regs + (offset << 2)); + } +#ifdef CONFIG_PPC_DCR + else + return dcr_read(drvdata->dcr_host, offset); +#endif + return 0; +} + static int xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi) @@ -271,6 +291,12 @@ static int xilinxfb_assign(struct platform_device *pdev, /* Tell the hardware where the frame buffer is */ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); + rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); + /* Endianess detection */ + if (rc != drvdata->fb_phys) { + drvdata->flags |= LITTLE_ENDIAN_ACCESS; + xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); + } /* Turn on the display */ drvdata->reg_ctrl_default = REG_CTRL_ENABLE;