From patchwork Mon Jun 3 10:13:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 2651711 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 7C37440D82 for ; Mon, 3 Jun 2013 10:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756615Ab3FCKNk (ORCPT ); Mon, 3 Jun 2013 06:13:40 -0400 Received: from mail-we0-f177.google.com ([74.125.82.177]:35828 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756515Ab3FCKNg (ORCPT ); Mon, 3 Jun 2013 06:13:36 -0400 Received: by mail-we0-f177.google.com with SMTP id m19so767033wev.36 for ; Mon, 03 Jun 2013 03:13:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:content-type:x-gm-message-state; bh=SrgAl1BbWEVvHpo4m5yATY4nmKPvbJrY2zCkjUL2oWQ=; b=TzQ1D2DUgC/qgWCIz6qfP92R24YkD9KQwHJ0V94JmRYNJ9z8oU6fpMsSAURecTgeBf SV+dab6rqdxGrQPsNX/pXgLKMMsd2clpr5tDIkc3lq9sFd2O4VmxWlEemYpCFsGbGwJP 7dseSk2qr/VhmW0IczA7W/Q9StsMQE5OJIc2BdUm9wXfUNqlOnVuYYiwThUaHhlUN3ce FwFENCfT/t5xVAnT3OYjT/rl5IzBQz0i6U4DSLu4WUu9K++ZmFQleVmKlGIIn9fU+Qs1 zT5OICjPTs9rBwmhFMfUzP0Z+MiBZN3MKToT86TGw+Repc7cmsU42CbYRkRD6VNEVrED z+3w== X-Received: by 10.194.216.105 with SMTP id op9mr18240612wjc.17.1370254415137; Mon, 03 Jun 2013 03:13:35 -0700 (PDT) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id d10sm22375343wik.0.2013.06.03.03.13.33 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 03 Jun 2013 03:13:33 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org Cc: Michal Simek , Michal Simek , Arnd Bergmann , Timur Tabi , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , linux-fbdev@vger.kernel.org Subject: [PATCH v4 3/7] video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG Date: Mon, 3 Jun 2013 12:13:18 +0200 Message-Id: X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQnAUXmiY0WHXd3udotxgP4ARMyJ63Bv8Wm8T/xmDQeOqDz6Heg0nIMKk7600mUAJKcwgOOy Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Using only PLB name is wrong for a long time because the same access functions are also used for AXI. s/PLB/BUS/g Signed-off-by: Michal Simek --- Changes in v4: None Changes in v3: - New patch in this patchset based on discussions Changes in v2: None drivers/video/xilinxfb.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 1.8.2.3 diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index c9b442b..d94c992 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -44,7 +44,7 @@ /* - * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for + * Xilinx calls it "TFT LCD Controller" though it can also be used for * the VGA port on the Xilinx ML40x board. This is a hardware display * controller for a 640x480 resolution TFT or VGA screen. * @@ -54,11 +54,11 @@ * don't start thinking about scrolling). The second allows the LCD to * be turned on or off as well as rotated 180 degrees. * - * In case of direct PLB access the second control register will be at + * In case of direct BUS access the second control register will be at * an offset of 4 as compared to the DCR access where the offset is 1 * i.e. REG_CTRL. So this is taken care in the function * xilinx_fb_out32 where it left shifts the offset 2 times in case of - * direct PLB access. + * direct BUS access. */ #define NUM_REGS 2 #define REG_FB_ADDR 0 @@ -116,7 +116,7 @@ static struct fb_var_screeninfo xilinx_fb_var = { }; -#define PLB_ACCESS_FLAG 0x1 /* 1 = PLB, 0 = DCR */ +#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ struct xilinxfb_drvdata { @@ -146,14 +146,14 @@ struct xilinxfb_drvdata { container_of(_info, struct xilinxfb_drvdata, info) /* - * The XPS TFT Controller can be accessed through PLB or DCR interface. + * The XPS TFT Controller can be accessed through BUS or DCR interface. * To perform the read/write on the registers we need to check on * which bus its connected and call the appropriate write API. */ static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, u32 val) { - if (drvdata->flags & PLB_ACCESS_FLAG) + if (drvdata->flags & BUS_ACCESS_FLAG) out_be32(drvdata->regs + (offset << 2), val); #ifdef CONFIG_PPC_DCR else @@ -235,10 +235,10 @@ static int xilinxfb_assign(struct device *dev, int rc; int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL; - if (drvdata->flags & PLB_ACCESS_FLAG) { + if (drvdata->flags & BUS_ACCESS_FLAG) { /* * Map the control registers in if the controller - * is on direct PLB interface. + * is on direct BUS interface. */ if (!request_mem_region(physaddr, 8, DRIVER_NAME)) { dev_err(dev, "Couldn't lock memory region at 0x%08lX\n", @@ -270,7 +270,7 @@ static int xilinxfb_assign(struct device *dev, if (!drvdata->fb_virt) { dev_err(dev, "Could not allocate frame buffer memory\n"); rc = -ENOMEM; - if (drvdata->flags & PLB_ACCESS_FLAG) + if (drvdata->flags & BUS_ACCESS_FLAG) goto err_fbmem; else goto err_region; @@ -323,7 +323,7 @@ static int xilinxfb_assign(struct device *dev, goto err_regfb; } - if (drvdata->flags & PLB_ACCESS_FLAG) { + if (drvdata->flags & BUS_ACCESS_FLAG) { /* Put a banner in the log (for DEBUG) */ dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs); @@ -348,11 +348,11 @@ err_cmap: xilinx_fb_out32(drvdata, REG_CTRL, 0); err_fbmem: - if (drvdata->flags & PLB_ACCESS_FLAG) + if (drvdata->flags & BUS_ACCESS_FLAG) iounmap(drvdata->regs); err_map: - if (drvdata->flags & PLB_ACCESS_FLAG) + if (drvdata->flags & BUS_ACCESS_FLAG) release_mem_region(physaddr, 8); err_region: @@ -384,7 +384,7 @@ static int xilinxfb_release(struct device *dev) xilinx_fb_out32(drvdata, REG_CTRL, 0); /* Release the resources, as allocated based on interface */ - if (drvdata->flags & PLB_ACCESS_FLAG) { + if (drvdata->flags & BUS_ACCESS_FLAG) { iounmap(drvdata->regs); release_mem_region(drvdata->regs_phys, 8); } @@ -423,18 +423,18 @@ static int xilinxfb_of_probe(struct platform_device *op) } /* - * To check whether the core is connected directly to DCR or PLB + * To check whether the core is connected directly to DCR or BUS * interface and initialize the tft_access accordingly. */ of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if", &tft_access); /* - * Fill the resource structure if its direct PLB interface + * Fill the resource structure if its direct BUS interface * otherwise fill the dcr_host structure. */ if (tft_access) { - drvdata->flags |= PLB_ACCESS_FLAG; + drvdata->flags |= BUS_ACCESS_FLAG; rc = of_address_to_resource(op->dev.of_node, 0, &res); if (rc) { dev_err(&op->dev, "invalid address\n");