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[0/2] fpga: dfl: optional VSEC for start of dfl

Message ID 20201117012552.262149-1-matthew.gerlach@linux.intel.com (mailing list archive)
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Series fpga: dfl: optional VSEC for start of dfl | expand

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Matthew Gerlach Nov. 17, 2020, 1:25 a.m. UTC 
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c.  This patchset
adds support for the start of one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space.  If no
such VSEC structure exists, then the start of the DFL is assumed to be 
Bar0/Offset 0 for backward compatibility.

Matthew Gerlach (2):
  fpga: dfl: refactor cci_enumerate_feature_devs()
  fpga: dfl: look for vendor specific capability

 Documentation/fpga/dfl.rst |  10 +++
 drivers/fpga/dfl-pci.c     | 168 +++++++++++++++++++++++++++++--------
 2 files changed, 143 insertions(+), 35 deletions(-)