From patchwork Wed Feb 15 00:31:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 9573147 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC0AA600F6 for ; Wed, 15 Feb 2017 00:32:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E7B127F81 for ; Wed, 15 Feb 2017 00:32:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92C5827FA8; Wed, 15 Feb 2017 00:32:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC0E727F95 for ; Wed, 15 Feb 2017 00:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751654AbdBOAbr (ORCPT ); Tue, 14 Feb 2017 19:31:47 -0500 Received: from mail.kernel.org ([198.145.29.136]:60426 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751618AbdBOAbo (ORCPT ); Tue, 14 Feb 2017 19:31:44 -0500 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F2405200D0; Wed, 15 Feb 2017 00:31:42 +0000 (UTC) Received: from tyrael.amer.corp.natinst.com (207-114-172-147.static.twtelecom.net [207.114.172.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9CBC620320; Wed, 15 Feb 2017 00:31:41 +0000 (UTC) From: mdf@kernel.org To: linux-fpga@vger.kernel.org Cc: mdf@kernel.org, Moritz Fischer , Alan Tull , Michal Simek , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-kernel@vger.kernel.org Subject: [PATCH 2/2] fpga: zynq: Add support for encrypted bitstreams Date: Tue, 14 Feb 2017 16:31:30 -0800 Message-Id: <1487118690-21166-2-git-send-email-mdf@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487118690-21166-1-git-send-email-mdf@kernel.org> References: <1487118690-21166-1-git-send-email-mdf@kernel.org> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Moritz Fischer Add support for encrypted bitstreams. For this to work the system must be booted in secure mode. In order for on-the-fly decryption to work, the PCAP clock rate needs to be lowered via the PCAP_RATE_EN bit. Signed-off-by: Moritz Fischer Cc: Alan Tull Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: linux-fpga@vger.kernel.org --- drivers/fpga/zynq-fpga.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index cb3caf5..52dabfc 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -72,6 +72,10 @@ #define CTRL_PCAP_PR_MASK BIT(27) /* Enable PCAP */ #define CTRL_PCAP_MODE_MASK BIT(26) +/* Lower rate to allow decrypt on the fly */ +#define CTRL_PCAP_RATE_EN_MASK BIT(25) +/* System booted in secure mode */ +#define CTRL_SEC_EN_MASK BIT(7) /* Miscellaneous Control Register bit definitions */ /* Internal PCAP loopback */ @@ -264,6 +268,17 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, if (err) return err; + /* check if bitstream is encrypted & and system's still secure */ + if (info->flags & FPGA_MGR_DECRYPT_BITSTREAM) { + ctrl = zynq_fpga_read(priv, CTRL_OFFSET); + if (!(ctrl & CTRL_SEC_EN_MASK)) { + dev_err(&mgr->dev, + "System not secure, can't use crypted bitstreams\n"); + err = -EINVAL; + goto out_err; + } + } + /* don't globally reset PL if we're doing partial reconfig */ if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { if (!zynq_fpga_has_sync(buf, count)) { @@ -335,12 +350,19 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* set configuration register with following options: * - enable PCAP interface - * - set throughput for maximum speed + * - set throughput for maximum speed (if bistream not crypted) * - set CPU in user mode */ ctrl = zynq_fpga_read(priv, CTRL_OFFSET); - zynq_fpga_write(priv, CTRL_OFFSET, - (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl)); + if (info->flags & FPGA_MGR_DECRYPT_BITSTREAM) + zynq_fpga_write(priv, CTRL_OFFSET, + (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK + | CTRL_PCAP_RATE_EN_MASK | ctrl)); + else + zynq_fpga_write(priv, CTRL_OFFSET, + (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK + | ctrl)); + /* We expect that the command queue is empty right now. */ status = zynq_fpga_read(priv, STATUS_OFFSET);