From patchwork Thu Mar 30 12:08:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wu, Hao" X-Patchwork-Id: 9654021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DE6D6034C for ; Thu, 30 Mar 2017 12:15:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C9042858C for ; Thu, 30 Mar 2017 12:15:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6150828595; Thu, 30 Mar 2017 12:15:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3ECE628591 for ; Thu, 30 Mar 2017 12:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933466AbdC3MPi (ORCPT ); Thu, 30 Mar 2017 08:15:38 -0400 Received: from mga02.intel.com ([134.134.136.20]:27696 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933648AbdC3MPf (ORCPT ); Thu, 30 Mar 2017 08:15:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490876134; x=1522412134; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ALsAzrdvnzBhSqz5IiWrqZRxfgiNyfgTVy9lP4vc5Uc=; b=xWH8jLENK3SBWg3+nKO24TNjTxylg2StYmzkWQpbGHSIEEIVvJ5Gt2Z+ uWCGto37heRo4uoaIqps3epw1trFBw==; Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2017 05:15:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,246,1486454400"; d="scan'208";a="840018091" Received: from hao-dev.bj.intel.com ([10.238.157.61]) by FMSMGA003.fm.intel.com with ESMTP; 30 Mar 2017 05:15:31 -0700 From: Wu Hao To: atull@kernel.org, moritz.fischer@ettus.com, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: luwei.kang@intel.com, yi.z.zhang@intel.com, hao.wu@intel.com, Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong Subject: [PATCH 03/16] fpga: intel: add FPGA PCIe device driver Date: Thu, 30 Mar 2017 20:08:03 +0800 Message-Id: <1490875696-15145-4-git-send-email-hao.wu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490875696-15145-1-git-send-email-hao.wu@intel.com> References: <1490875696-15145-1-git-send-email-hao.wu@intel.com> Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhang Yi The Intel FPGA device appears as a PCIe device on the system. This patch implements the basic framework of the driver for Intel PCIe device which locates between CPU and Accelerated Function Units (AFUs). Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Zhang Yi Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao --- drivers/fpga/Kconfig | 2 + drivers/fpga/Makefile | 3 + drivers/fpga/intel/Kconfig | 27 +++++++++ drivers/fpga/intel/LICENSE.BSD | 24 ++++++++ drivers/fpga/intel/Makefile | 3 + drivers/fpga/intel/pcie.c | 129 +++++++++++++++++++++++++++++++++++++++++ 6 files changed, 188 insertions(+) create mode 100644 drivers/fpga/intel/Kconfig create mode 100644 drivers/fpga/intel/LICENSE.BSD create mode 100644 drivers/fpga/intel/Makefile create mode 100644 drivers/fpga/intel/pcie.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index d99b640..4e49aee 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -69,6 +69,8 @@ config ALTERA_FREEZE_BRIDGE isolate one region of the FPGA from the busses while that region is being reprogrammed. +source "drivers/fpga/intel/Kconfig" + endif # FPGA endmenu diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 53a41d2..46f1a5d 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -20,3 +20,6 @@ obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o + +# Intel FPGA Support +obj-$(CONFIG_INTEL_FPGA) += intel/ diff --git a/drivers/fpga/intel/Kconfig b/drivers/fpga/intel/Kconfig new file mode 100644 index 0000000..bf402f3 --- /dev/null +++ b/drivers/fpga/intel/Kconfig @@ -0,0 +1,27 @@ +menuconfig INTEL_FPGA + tristate "Intel(R) FPGA support" + depends on FPGA_DEVICE + help + Select this option to enable driver support for Intel(R) + Field-Programmable Gate Array (FPGA) solutions. This driver + provides interfaces for userspace applications to configure, + enumerate, open, and access FPGA accelerators on platforms + equipped with Intel(R) FPGA solutions and enables system + level management functions such as FPGA reconfiguration, + power management, and virtualization. + + Say Y if your platform has this technology. Say N if unsure. + +if INTEL_FPGA + +config INTEL_FPGA_PCI + tristate "Intel FPGA PCIe Driver" + depends on PCI + help + This is the driver for the PCIe device which locates between + CPU and Accelerated Function Units (AFUs) and allows them to + communicate with each other. + + To compile this as a module, choose M here. + +endif diff --git a/drivers/fpga/intel/LICENSE.BSD b/drivers/fpga/intel/LICENSE.BSD new file mode 100644 index 0000000..309d2b7 --- /dev/null +++ b/drivers/fpga/intel/LICENSE.BSD @@ -0,0 +1,24 @@ +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/drivers/fpga/intel/Makefile b/drivers/fpga/intel/Makefile new file mode 100644 index 0000000..61fd8ea --- /dev/null +++ b/drivers/fpga/intel/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_INTEL_FPGA_PCI) += intel-fpga-pci.o + +intel-fpga-pci-objs := pcie.o diff --git a/drivers/fpga/intel/pcie.c b/drivers/fpga/intel/pcie.c new file mode 100644 index 0000000..132d9da --- /dev/null +++ b/drivers/fpga/intel/pcie.c @@ -0,0 +1,129 @@ +/* + * Driver for Intel FPGA PCIe device + * + * Copyright (C) 2017 Intel Corporation, Inc. + * + * Authors: + * Zhang Yi + * Xiao Guangrong + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Henry Mitchel + * + * This work is licensed under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. See the + * LICENSE.BSD file under this directory for the BSD license and see + * the COPYING file in the top-level directory for the GPLv2 license. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRV_VERSION "EXPERIMENTAL VERSION" +#define DRV_NAME "intel-fpga-pci" + +/* PCI Device ID */ +#define PCIe_DEVICE_ID_PF_INT_5_X 0xBCBD +#define PCIe_DEVICE_ID_PF_INT_6_X 0xBCC0 +#define PCIe_DEVICE_ID_PF_DSC_1_X 0x09C4 +/* VF Device */ +#define PCIe_DEVICE_ID_VF_INT_5_X 0xBCBF +#define PCIe_DEVICE_ID_VF_INT_6_X 0xBCC1 +#define PCIe_DEVICE_ID_VF_DSC_1_X 0x09C5 + +static struct pci_device_id cci_pcie_id_tbl[] = { + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_PF_INT_5_X),}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_INT_5_X),}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_PF_INT_6_X),}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_INT_6_X),}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_PF_DSC_1_X),}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_DSC_1_X),}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); + +static +int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) +{ + int ret; + + ret = pci_enable_device(pcidev); + if (ret < 0) { + dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret); + goto exit; + } + + ret = pci_enable_pcie_error_reporting(pcidev); + if (ret && ret != -EINVAL) + dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret); + + ret = pci_request_regions(pcidev, DRV_NAME); + if (ret) { + dev_err(&pcidev->dev, "Failed to request regions.\n"); + goto disable_error_report_exit; + } + + pci_set_master(pcidev); + pci_save_state(pcidev); + + if (!dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64))) { + dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)); + } else if (!dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32))) { + dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)); + } else { + ret = -EIO; + dev_err(&pcidev->dev, "No suitable DMA support available.\n"); + goto release_region_exit; + } + + /* TODO: create and add the platform device per feature list */ + return 0; + +release_region_exit: + pci_release_regions(pcidev); +disable_error_report_exit: + pci_disable_pcie_error_reporting(pcidev); + pci_disable_device(pcidev); +exit: + return ret; +} + +static void cci_pci_remove(struct pci_dev *pcidev) +{ + pci_release_regions(pcidev); + pci_disable_pcie_error_reporting(pcidev); + pci_disable_device(pcidev); +} + +static struct pci_driver cci_pci_driver = { + .name = DRV_NAME, + .id_table = cci_pcie_id_tbl, + .probe = cci_pci_probe, + .remove = cci_pci_remove, +}; + +static int __init ccidrv_init(void) +{ + pr_info("Intel(R) FPGA PCIe Driver: Version %s\n", DRV_VERSION); + + return pci_register_driver(&cci_pci_driver); +} + +static void __exit ccidrv_exit(void) +{ + pci_unregister_driver(&cci_pci_driver); +} + +module_init(ccidrv_init); +module_exit(ccidrv_exit); + +MODULE_DESCRIPTION("Intel FPGA PCIe Device Driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("Dual BSD/GPL");