From patchwork Mon Nov 27 06:42:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wu, Hao" X-Patchwork-Id: 10075917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2E5DA60353 for ; Mon, 27 Nov 2017 06:55:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D5C9205D6 for ; Mon, 27 Nov 2017 06:55:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1204928CF2; Mon, 27 Nov 2017 06:55:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90666205D6 for ; Mon, 27 Nov 2017 06:55:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751475AbdK0Gzk (ORCPT ); Mon, 27 Nov 2017 01:55:40 -0500 Received: from mga14.intel.com ([192.55.52.115]:50513 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751746AbdK0Gwn (ORCPT ); Mon, 27 Nov 2017 01:52:43 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Nov 2017 22:52:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,463,1505804400"; d="scan'208";a="178125108" Received: from hao-dev.bj.intel.com ([10.238.157.61]) by orsmga005.jf.intel.com with ESMTP; 26 Nov 2017 22:52:39 -0800 From: Wu Hao To: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-api@vger.kernel.org, luwei.kang@intel.com, yi.z.zhang@intel.com, hao.wu@intel.com, Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong Subject: [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Date: Mon, 27 Nov 2017 14:42:18 +0800 Message-Id: <1511764948-20972-12-git-send-email-hao.wu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511764948-20972-1-git-send-email-hao.wu@intel.com> References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kang Luwei The header register set is always present for FPGA Management Engine (FME), this patch implements init and uinit function for header sub feature and introduce several read-only sysfs interfaces for the capability and status. Sysfs interfaces: * /sys/class/fpga_region///ports_num Read-only. Number of ports implemented * /sys/class/fpga_region///bitstream_id Read-only. Blue Bitstream (static FPGA region) identifier number * /sys/class/fpga_region///bitstream_metadata Read-only. Blue Bitstream (static FPGA region) meta data Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Kang Luwei Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao ---- v2: add sysfs documentation v3: rename driver to fpga-dfl-fme. improve sysfs doc and commit description. replace bitfield. --- .../ABI/testing/sysfs-platform-fpga-dfl-fme | 21 ++++++++ drivers/fpga/dfl-fme-main.c | 60 ++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme diff --git a/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme new file mode 100644 index 0000000..6b32799 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme @@ -0,0 +1,21 @@ +What: /sys/bus/platform/devices/fpga-dfl-fme.0/ports_num +Date: November 2017 +KernelVersion: 4.15 +Contact: Wu Hao +Description: Read-only. One DFL FPGA device may have more than 1 + port/Accelerator Function Unit (AFU). It returns the + number of ports on the FPGA device when read it. + +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_id +Date: November 2017 +KernelVersion: 4.15 +Contact: Wu Hao +Description: Read-only. It returns Blue Bitstream (static FPGA region) + identifier number. + +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_meta +Date: November 2017 +KernelVersion: 4.15 +Contact: Wu Hao +Description: Read-only. It returns Blue Bitstream (static FPGA region) + meta data. diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index f7b5f7d..d17c66a 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -21,9 +21,68 @@ #include "fpga-dfl.h" +static ssize_t ports_num_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + void __iomem *base; + u64 v; + + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); + + v = readq(base + FME_HDR_CAP); + + return scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v)); +} +static DEVICE_ATTR_RO(ports_num); + +static ssize_t bitstream_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + void __iomem *base; + u64 v; + + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); + + v = readq(base + FME_HDR_BITSTREAM_ID); + + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); +} +static DEVICE_ATTR_RO(bitstream_id); + +static ssize_t bitstream_metadata_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + void __iomem *base; + u64 v; + + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); + + v = readq(base + FME_HDR_BITSTREAM_MD); + + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); +} +static DEVICE_ATTR_RO(bitstream_metadata); + +static const struct attribute *fme_hdr_attrs[] = { + &dev_attr_ports_num.attr, + &dev_attr_bitstream_id.attr, + &dev_attr_bitstream_metadata.attr, + NULL, +}; + static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) { + void __iomem *base = feature->ioaddr; + int ret; + dev_dbg(&pdev->dev, "FME HDR Init.\n"); + dev_dbg(&pdev->dev, "FME cap %llx.\n", + (unsigned long long)readq(base + FME_HDR_CAP)); + + ret = sysfs_create_files(&pdev->dev.kobj, fme_hdr_attrs); + if (ret) + return ret; return 0; } @@ -31,6 +90,7 @@ static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) static void fme_hdr_uinit(struct platform_device *pdev, struct feature *feature) { dev_dbg(&pdev->dev, "FME HDR UInit.\n"); + sysfs_remove_files(&pdev->dev.kobj, fme_hdr_attrs); } static const struct feature_ops fme_hdr_ops = {