| Message ID | 1611110606-10380-3-git-send-email-yilun.xu@intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | UIO support for dfl devices | expand |
Doc suggestions: On 1/19/21 6:43 PM, Xu Yilun wrote: > This patch adds description for UIO support for dfl devices on DFL > bus. > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > --- > v2: no doc in v1, add it for v2. > v3: some documentation fixes. > v4: documentation change since the driver matching is changed. > v5: no change. > v6: improve the title of the userspace driver support section. > some word improvement. > v7: rebased to next-20210119 > --- > Documentation/fpga/dfl.rst | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index c41ac76..f96a6fb 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -7,6 +7,7 @@ Authors: > - Enno Luebbers <enno.luebbers@intel.com> > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > - Wu Hao <hao.wu@intel.com> > +- Xu Yilun <yilun.xu@intel.com> > > The Device Feature List (DFL) FPGA framework (and drivers according to > this framework) hides the very details of low layer hardwares and provides > @@ -530,6 +531,30 @@ Being able to specify more than one DFL per BAR has been considered, but it > was determined the use case did not provide value. Specifying a single DFL > per BAR simplifies the implementation and allows for extra error checking. > > + > +Userspace driver support for DFL devices > +======================================== > +The purpose of an FPGA is to be reprogrammed with newly developed hardware > +components. New hardware can instantiate a new private feature in the DFL, and > +then get a DFL device in their system. In some cases users may need a userspace then present a DFL device in the system. > +driver for the DFL device: > + > +* Users may need to run some diagnostic test for their hardwares. hardware. > +* Users may prototype the kernel driver in user space. > +* Some hardware is designed for specific purposes and does not fit into one of > + the standard kernel subsystems. > + > +This requires direct access to MMIO space and interrupt handling from > +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this > +purpose. It adds the uio_pdrv_genirq platform device with the resources of > +the DFL feature, and lets the generic UIO platform device driver provide UIO > +support to userspace. > + > +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. > +To support a new DFL feature been directly accessed via UIO, its feature id To support a new DFL feature via UIO direct access, its feature id > +should be added to the driver's id_table. > + > + > Open discussion > =============== > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration > HTH.
On Tue, Jan 19, 2021 at 07:12:24PM -0800, Randy Dunlap wrote: > Doc suggestions: > > On 1/19/21 6:43 PM, Xu Yilun wrote: > > This patch adds description for UIO support for dfl devices on DFL > > bus. > > > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > > --- > > v2: no doc in v1, add it for v2. > > v3: some documentation fixes. > > v4: documentation change since the driver matching is changed. > > v5: no change. > > v6: improve the title of the userspace driver support section. > > some word improvement. > > v7: rebased to next-20210119 > > --- > > Documentation/fpga/dfl.rst | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index c41ac76..f96a6fb 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -7,6 +7,7 @@ Authors: > > - Enno Luebbers <enno.luebbers@intel.com> > > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > > - Wu Hao <hao.wu@intel.com> > > +- Xu Yilun <yilun.xu@intel.com> > > > > The Device Feature List (DFL) FPGA framework (and drivers according to > > this framework) hides the very details of low layer hardwares and provides > > @@ -530,6 +531,30 @@ Being able to specify more than one DFL per BAR has been considered, but it > > was determined the use case did not provide value. Specifying a single DFL > > per BAR simplifies the implementation and allows for extra error checking. > > > > + > > +Userspace driver support for DFL devices > > +======================================== > > +The purpose of an FPGA is to be reprogrammed with newly developed hardware > > +components. New hardware can instantiate a new private feature in the DFL, and > > +then get a DFL device in their system. In some cases users may need a userspace > > then present a DFL device in the system. > > > +driver for the DFL device: > > + > > +* Users may need to run some diagnostic test for their hardwares. > > hardware. > > > +* Users may prototype the kernel driver in user space. > > +* Some hardware is designed for specific purposes and does not fit into one of > > + the standard kernel subsystems. > > + > > +This requires direct access to MMIO space and interrupt handling from > > +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this > > +purpose. It adds the uio_pdrv_genirq platform device with the resources of > > +the DFL feature, and lets the generic UIO platform device driver provide UIO > > +support to userspace. > > + > > +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. > > +To support a new DFL feature been directly accessed via UIO, its feature id > > To support a new DFL feature via UIO direct access, its feature id Thanks for the fixes. Will fix them all. Yilun
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index c41ac76..f96a6fb 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -7,6 +7,7 @@ Authors: - Enno Luebbers <enno.luebbers@intel.com> - Xiao Guangrong <guangrong.xiao@linux.intel.com> - Wu Hao <hao.wu@intel.com> +- Xu Yilun <yilun.xu@intel.com> The Device Feature List (DFL) FPGA framework (and drivers according to this framework) hides the very details of low layer hardwares and provides @@ -530,6 +531,30 @@ Being able to specify more than one DFL per BAR has been considered, but it was determined the use case did not provide value. Specifying a single DFL per BAR simplifies the implementation and allows for extra error checking. + +Userspace driver support for DFL devices +======================================== +The purpose of an FPGA is to be reprogrammed with newly developed hardware +components. New hardware can instantiate a new private feature in the DFL, and +then get a DFL device in their system. In some cases users may need a userspace +driver for the DFL device: + +* Users may need to run some diagnostic test for their hardwares. +* Users may prototype the kernel driver in user space. +* Some hardware is designed for specific purposes and does not fit into one of + the standard kernel subsystems. + +This requires direct access to MMIO space and interrupt handling from +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this +purpose. It adds the uio_pdrv_genirq platform device with the resources of +the DFL feature, and lets the generic UIO platform device driver provide UIO +support to userspace. + +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. +To support a new DFL feature been directly accessed via UIO, its feature id +should be added to the driver's id_table. + + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
This patch adds description for UIO support for dfl devices on DFL bus. Signed-off-by: Xu Yilun <yilun.xu@intel.com> --- v2: no doc in v1, add it for v2. v3: some documentation fixes. v4: documentation change since the driver matching is changed. v5: no change. v6: improve the title of the userspace driver support section. some word improvement. v7: rebased to next-20210119 --- Documentation/fpga/dfl.rst | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)