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[v8,2/2] Documentation: fpga: dfl: Add description for DFL UIO support

Message ID 1611218085-28269-3-git-send-email-yilun.xu@intel.com (mailing list archive)
State Superseded
Headers show
Series UIO support for dfl devices | expand

Commit Message

Xu Yilun Jan. 21, 2021, 8:34 a.m. UTC
This patch adds description for UIO support for dfl devices on DFL

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support section.
    some word improvement.
v7: rebased to next-20210119
v8: some doc fixes.
 Documentation/fpga/dfl.rst | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
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diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index c41ac76..14b8413 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -7,6 +7,7 @@  Authors:
 - Enno Luebbers <enno.luebbers@intel.com>
 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
 - Wu Hao <hao.wu@intel.com>
+- Xu Yilun <yilun.xu@intel.com>
 The Device Feature List (DFL) FPGA framework (and drivers according to
 this framework) hides the very details of low layer hardwares and provides
@@ -530,6 +531,30 @@  Being able to specify more than one DFL per BAR has been considered, but it
 was determined the use case did not provide value.  Specifying a single DFL
 per BAR simplifies the implementation and allows for extra error checking.
+Userspace driver support for DFL devices
+The purpose of an FPGA is to be reprogrammed with newly developed hardware
+components. New hardware can instantiate a new private feature in the DFL, and
+then present a DFL device in the system. In some cases users may need a
+userspace driver for the DFL device:
+* Users may need to run some diagnostic test for their hardware.
+* Users may prototype the kernel driver in user space.
+* Some hardware is designed for specific purposes and does not fit into one of
+  the standard kernel subsystems.
+This requires direct access to MMIO space and interrupt handling from
+userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this
+purpose. It adds the uio_pdrv_genirq platform device with the resources of
+the DFL feature, and lets the generic UIO platform device driver provide UIO
+support to userspace.
+FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver.
+To support a new DFL feature via UIO direct access, its feature id should be
+added to the driver's id_table.
 Open discussion
 FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration