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[v2,2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

Message ID 20181025073206.9264-3-nava.manne@xilinx.com (mailing list archive)
State Superseded
Headers show
Series Add Bitstream configuration support for ZynqMP | expand

Commit Message

Nava kishore Manne Oct. 25, 2018, 7:32 a.m. UTC
Add documentation to describe Xilinx ZynqMP fpga driver

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Changes for v2:
		-Removed "----" separators.
Changes for v1:
                -Created a Seperate(New) DT binding file as
                 suggested by Rob.

Changes for RFC-V2:
                -Moved pcap node as a child to firwmare
                 node as suggested by Rob.

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
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diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@ 
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};