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Tue, 26 Mar 2019 07:31:40 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1h8n71-0002xg-Ek; Tue, 26 Mar 2019 07:31:35 -0700 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x2QEVT6P031972; Tue, 26 Mar 2019 07:31:29 -0700 Received: from [172.23.37.118] (helo=xhdnavam40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1h8n6v-0002t5-7Z; Tue, 26 Mar 2019 07:31:29 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , CC: Rajan Vaja Subject: [PATCH v5 1/6] dt-bindings: power: Add ZynqMP power domain bindings Date: Tue, 26 Mar 2019 20:01:24 +0530 Message-ID: <20190326143129.2608-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190326143129.2608-1-nava.manne@xilinx.com> References: <20190326143129.2608-1-nava.manne@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(136003)(39860400002)(396003)(376002)(2980300002)(199004)(189003)(486006)(126002)(476003)(47776003)(5660300002)(77096007)(478600001)(2201001)(305945005)(4326008)(2616005)(8936002)(316002)(51416003)(7696005)(106002)(107886003)(50226002)(76176011)(110136005)(16586007)(26005)(9786002)(106466001)(11346002)(356004)(2906002)(6666004)(426003)(36386004)(81166006)(50466002)(48376002)(446003)(81156014)(8676002)(63266004)(36756003)(336012)(1076003)(186003)(921003)(2101003)(1121003)(83996005);DIR:OUT;SFP:1101;SCL:1;SRVR:BN7PR02MB5235;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Reviewed-by: Rob Herring --- .../bindings/power/xlnx,zynqmp-genpd.txt | 34 ++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt new file mode 100644 index 000000000000..3c7f2378e146 --- /dev/null +++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt @@ -0,0 +1,34 @@ +----------------------------------------------------------- +Device Tree Bindings for the Xilinx Zynq MPSoC PM domains +----------------------------------------------------------- +The binding for zynqmp-power-controller follow the common +generic PM domain binding[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +== Zynq MPSoC Generic PM Domain Node == + +Required property: + - Below property should be in zynqmp-firmware node. + - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1. + +Power domain ID indexes are mentioned in +include/dt-bindings/power/xlnx-zynqmp-power.h. + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + ... + #power-domain-cells = <1>; + ... + }; +}; + +sata { + ... + power-domains = <&zynqmp_firmware 2>; + ... +}; diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h new file mode 100644 index 000000000000..1bc9636098ca --- /dev/null +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +#define _DT_BINDINGS_ZYNQMP_POWER_H + +#define PD_USB_0 0 +#define PD_USB_1 1 +#define PD_SATA 2 +#define PD_SPI_0 3 +#define PD_SPI_1 4 +#define PD_UART_0 5 +#define PD_UART_1 6 +#define PD_ETH_0 7 +#define PD_ETH_1 8 +#define PD_ETH_2 9 +#define PD_ETH_3 10 +#define PD_I2C_0 11 +#define PD_I2C_1 12 +#define PD_DP 13 +#define PD_GDMA 14 +#define PD_ADMA 15 +#define PD_TTC_0 16 +#define PD_TTC_1 17 +#define PD_TTC_2 18 +#define PD_TTC_3 19 +#define PD_SD_0 20 +#define PD_SD_1 21 +#define PD_NAND 22 +#define PD_QSPI 23 +#define PD_GPIO 24 +#define PD_CAN_0 25 +#define PD_CAN_1 26 +#define PD_PCIE 27 +#define PD_GPU 28 + +#endif