From patchwork Fri Oct 9 01:14:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 11824833 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEB0F1592 for ; Fri, 9 Oct 2020 01:14:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 984D822257 for ; Fri, 9 Oct 2020 01:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730462AbgJIBOh (ORCPT ); Thu, 8 Oct 2020 21:14:37 -0400 Received: from mga17.intel.com ([192.55.52.151]:13074 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730243AbgJIBOa (ORCPT ); Thu, 8 Oct 2020 21:14:30 -0400 IronPort-SDR: JPxtM42IoJ0iD1pU4yngPdfd1cL9jSXnQNyxMf46B8K+aaP8AIV/bHzvKTKLpJNBgTKu7DqzvG ihlLj0twrBgw== X-IronPort-AV: E=McAfee;i="6000,8403,9768"; a="145294137" X-IronPort-AV: E=Sophos;i="5.77,353,1596524400"; d="scan'208";a="145294137" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 18:14:30 -0700 IronPort-SDR: nz3MGVMninc0PkqvdR+0K7x7Z1wMtIhYVUnbuW7MIACQh4FhUot0zQ8c0jTd1xIr+gSwzq3Cqp 8tRJ3GI+62hg== X-IronPort-AV: E=Sophos;i="5.77,353,1596524400"; d="scan'208";a="462002353" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.254.33.152]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 18:14:29 -0700 From: Russ Weight To: mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight Subject: [PATCH v3 3/6] fpga: m10bmc-sec: expose max10 flash update counts Date: Thu, 8 Oct 2020 18:14:20 -0700 Message-Id: <20201009011423.22741-4-russell.h.weight@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201009011423.22741-1-russell.h.weight@intel.com> References: <20201009011423.22741-1-russell.h.weight@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the MAX10 BMC Secure Update driver to provide a handler to expose the flash update count for the FPGA user image in sysfs. Signed-off-by: Russ Weight Reviewed-by: Tom Rix --- v3: - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update driver" - Removed wrapper functions (m10bmc_raw_*, m10bmc_sys_*). The underlying functions are now called directly. v2: - Renamed get_qspi_flash_count() to m10bmc_user_flash_count() - Minor code cleanup per review comments - Added m10bmc_ prefix to functions in m10bmc_iops structure --- drivers/fpga/intel-m10-bmc-secure.c | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c index 433af08a9507..e1fb7f7aa3e2 100644 --- a/drivers/fpga/intel-m10-bmc-secure.c +++ b/drivers/fpga/intel-m10-bmc-secure.c @@ -11,6 +11,7 @@ #include #include #include +#include #include struct m10bmc_sec { @@ -106,7 +107,39 @@ static int m10bmc_pr_reh(struct fpga_sec_mgr *smgr, u8 *hash, return m10bmc_reh(smgr, PR_REH_ADDR, hash, size); } +#define FLASH_COUNT_SIZE 4096 /* count stored in inverted bit vector */ + +static int m10bmc_user_flash_count(struct fpga_sec_mgr *smgr) +{ + struct m10bmc_sec *sec = smgr->priv; + unsigned int stride = regmap_get_reg_stride(sec->m10bmc->regmap); + unsigned int num_bits = FLASH_COUNT_SIZE * 8; + u8 *flash_buf; + int ret; + + flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL); + if (!flash_buf) + return -ENOMEM; + + ret = regmap_bulk_read(sec->m10bmc->regmap, USER_FLASH_COUNT, + flash_buf, FLASH_COUNT_SIZE / stride); + if (ret) { + dev_err(sec->dev, + "failed to read flash count: %x cnt %x: %d\n", + USER_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret); + goto exit_free; + } + + ret = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits); + +exit_free: + kfree(flash_buf); + + return ret; +} + static const struct fpga_sec_mgr_ops m10bmc_sops = { + .user_flash_count = m10bmc_user_flash_count, .bmc_root_entry_hash = m10bmc_bmc_reh, .sr_root_entry_hash = m10bmc_sr_reh, .pr_root_entry_hash = m10bmc_pr_reh,