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Tue, 23 Mar 2021 22:35:46 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.72.212] (port=51054 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lOwBG-0006E8-Sk; Tue, 23 Mar 2021 22:35:46 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id 0D2E9600130; Tue, 23 Mar 2021 22:29:57 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V4 XRT Alveo 17/20] fpga: xrt: clock frequency counter platform driver Date: Tue, 23 Mar 2021 22:29:44 -0700 Message-ID: <20210324052947.27889-18-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210324052947.27889-1-lizhi.hou@xilinx.com> References: <20210324052947.27889-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e97b36d2-102e-4410-f311-08d8ee86b667 X-MS-TrafficTypeDiagnostic: MW4PR02MB7378: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2021 05:36:02.5399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e97b36d2-102e-4410-f311-08d8ee86b667 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR02MB7378 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add clock frequency counter driver. Clock frequency counter is a hardware function discovered by walking xclbin metadata. A platform device node will be created for it. Other part of driver can read the actual clock frequency through clock frequency counter driver. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/include/xleaf/clkfreq.h | 21 ++ drivers/fpga/xrt/lib/xleaf/clkfreq.c | 240 +++++++++++++++++++++++ 2 files changed, 261 insertions(+) create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c diff --git a/drivers/fpga/xrt/include/xleaf/clkfreq.h b/drivers/fpga/xrt/include/xleaf/clkfreq.h new file mode 100644 index 000000000000..005441d5df78 --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf/clkfreq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_CLKFREQ_H_ +#define _XRT_CLKFREQ_H_ + +#include "xleaf.h" + +/* + * CLKFREQ driver leaf calls. + */ +enum xrt_clkfreq_leaf_cmd { + XRT_CLKFREQ_READ = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ +}; + +#endif /* _XRT_CLKFREQ_H_ */ diff --git a/drivers/fpga/xrt/lib/xleaf/clkfreq.c b/drivers/fpga/xrt/lib/xleaf/clkfreq.c new file mode 100644 index 000000000000..49473adde3fd --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/clkfreq.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA Clock Frequency Counter Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/clkfreq.h" + +#define CLKFREQ_ERR(clkfreq, fmt, arg...) \ + xrt_err((clkfreq)->pdev, fmt "\n", ##arg) +#define CLKFREQ_WARN(clkfreq, fmt, arg...) \ + xrt_warn((clkfreq)->pdev, fmt "\n", ##arg) +#define CLKFREQ_INFO(clkfreq, fmt, arg...) \ + xrt_info((clkfreq)->pdev, fmt "\n", ##arg) +#define CLKFREQ_DBG(clkfreq, fmt, arg...) \ + xrt_dbg((clkfreq)->pdev, fmt "\n", ##arg) + +#define XRT_CLKFREQ "xrt_clkfreq" + +#define XRT_CLKFREQ_CONTROL_STATUS_MASK 0xffff + +#define XRT_CLKFREQ_CONTROL_START 0x1 +#define XRT_CLKFREQ_CONTROL_DONE 0x2 +#define XRT_CLKFREQ_V5_CLK0_ENABLED 0x10000 + +#define XRT_CLKFREQ_CONTROL_REG 0 +#define XRT_CLKFREQ_COUNT_REG 0x8 +#define XRT_CLKFREQ_V5_COUNT_REG 0x10 + +#define XRT_CLKFREQ_READ_RETRIES 10 + +static const struct regmap_config clkfreq_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x1000, +}; + +struct clkfreq { + struct platform_device *pdev; + struct regmap *regmap; + const char *clkfreq_ep_name; + struct mutex clkfreq_lock; /* clock counter dev lock */ +}; + +static int clkfreq_read(struct clkfreq *clkfreq, u32 *freq) +{ + int times = XRT_CLKFREQ_READ_RETRIES; + u32 status; + int ret; + + *freq = 0; + mutex_lock(&clkfreq->clkfreq_lock); + ret = regmap_write(clkfreq->regmap, XRT_CLKFREQ_CONTROL_REG, XRT_CLKFREQ_CONTROL_START); + if (ret) { + CLKFREQ_INFO(clkfreq, "write start to control reg failed %d", ret); + goto failed; + } + while (times != 0) { + ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_CONTROL_REG, &status); + if (ret) { + CLKFREQ_INFO(clkfreq, "read control reg failed %d", ret); + goto failed; + } + if ((status & XRT_CLKFREQ_CONTROL_STATUS_MASK) == XRT_CLKFREQ_CONTROL_DONE) + break; + mdelay(1); + times--; + }; + + if (!times) { + ret = -ETIMEDOUT; + goto failed; + } + + if (status & XRT_CLKFREQ_V5_CLK0_ENABLED) + ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_V5_COUNT_REG, freq); + else + ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_COUNT_REG, freq); + if (ret) { + CLKFREQ_INFO(clkfreq, "read count failed %d", ret); + goto failed; + } + + mutex_unlock(&clkfreq->clkfreq_lock); + + return 0; + +failed: + mutex_unlock(&clkfreq->clkfreq_lock); + + return ret; +} + +static ssize_t freq_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct clkfreq *clkfreq = platform_get_drvdata(to_platform_device(dev)); + ssize_t count; + u32 freq; + + if (clkfreq_read(clkfreq, &freq)) + return -EINVAL; + + count = snprintf(buf, 64, "%u\n", freq); + + return count; +} +static DEVICE_ATTR_RO(freq); + +static struct attribute *clkfreq_attrs[] = { + &dev_attr_freq.attr, + NULL, +}; + +static struct attribute_group clkfreq_attr_group = { + .attrs = clkfreq_attrs, +}; + +static int +xrt_clkfreq_leaf_call(struct platform_device *pdev, u32 cmd, void *arg) +{ + struct clkfreq *clkfreq; + int ret = 0; + + clkfreq = platform_get_drvdata(pdev); + + switch (cmd) { + case XRT_XLEAF_EVENT: + /* Does not handle any event. */ + break; + case XRT_CLKFREQ_READ: + ret = clkfreq_read(clkfreq, arg); + break; + default: + xrt_err(pdev, "unsupported cmd %d", cmd); + return -EINVAL; + } + + return ret; +} + +static int clkfreq_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, &clkfreq_attr_group); + + return 0; +} + +static int clkfreq_probe(struct platform_device *pdev) +{ + struct clkfreq *clkfreq = NULL; + void __iomem *base = NULL; + struct resource *res; + int ret; + + clkfreq = devm_kzalloc(&pdev->dev, sizeof(*clkfreq), GFP_KERNEL); + if (!clkfreq) + return -ENOMEM; + + platform_set_drvdata(pdev, clkfreq); + clkfreq->pdev = pdev; + mutex_init(&clkfreq->clkfreq_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -EINVAL; + goto failed; + } + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto failed; + } + + clkfreq->regmap = devm_regmap_init_mmio(&pdev->dev, base, &clkfreq_regmap_config); + if (IS_ERR(clkfreq->regmap)) { + CLKFREQ_ERR(clkfreq, "regmap %pR failed", res); + ret = PTR_ERR(clkfreq->regmap); + goto failed; + } + clkfreq->clkfreq_ep_name = res->name; + + ret = sysfs_create_group(&pdev->dev.kobj, &clkfreq_attr_group); + if (ret) { + CLKFREQ_ERR(clkfreq, "create clkfreq attrs failed: %d", ret); + goto failed; + } + + CLKFREQ_INFO(clkfreq, "successfully initialized clkfreq subdev"); + + return 0; + +failed: + return ret; +} + +static struct xrt_subdev_endpoints xrt_clkfreq_endpoints[] = { + { + .xse_names = (struct xrt_subdev_ep_names[]) { + { .regmap_name = XRT_MD_REGMAP_CLKFREQ }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_subdev_drvdata xrt_clkfreq_data = { + .xsd_dev_ops = { + .xsd_leaf_call = xrt_clkfreq_leaf_call, + }, +}; + +static const struct platform_device_id xrt_clkfreq_table[] = { + { XRT_CLKFREQ, (kernel_ulong_t)&xrt_clkfreq_data }, + { }, +}; + +static struct platform_driver xrt_clkfreq_driver = { + .driver = { + .name = XRT_CLKFREQ, + }, + .probe = clkfreq_probe, + .remove = clkfreq_remove, + .id_table = xrt_clkfreq_table, +}; + +XRT_LEAF_INIT_FINI_FUNC(XRT_SUBDEV_CLKFREQ, clkfreq);