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Fri, 2 Apr 2021 02:28:51 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [10.140.6.60] (port=58326 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lSG6j-0005gX-To; Fri, 02 Apr 2021 02:28:50 -0700 From: Nava kishore Manne To: , , , , , , , , , Subject: [PATCH 2/3] fpga: region: Add fpga-region property 'power-domains' Date: Fri, 2 Apr 2021 14:50:48 +0530 Message-ID: <20210402092049.479-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210402092049.479-1-nava.manne@xilinx.com> References: <20210402092049.479-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f78da796-3174-4eec-e3ac-08d8f5b9bd8d X-MS-TrafficTypeDiagnostic: SN6PR02MB5341: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2021 09:28:57.0063 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f78da796-3174-4eec-e3ac-08d8f5b9bd8d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5341 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add fpga-region property 'power-domains' to allow to handle the FPGA/PL power domins. dt-bindings: fpga: Enable PM generic domain support Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index e811cf825019..969ca53bb65e 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during