| Message ID | 20210427205431.23896-21-lizhi.hou@xilinx.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | XRT Alveo driver overview | expand |
Hi Lizhi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linux/master]
[also build test WARNING on linus/master v5.12 next-20210427]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lizhi-Hou/XRT-Alveo-driver-overview/20210428-050424
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 1fe5501ba1abf2b7e78295df73675423bd6899a0
config: x86_64-randconfig-s032-20210428 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/079fb263b22e0d961ac204b3928bdff5d8ebf3d5
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Lizhi-Hou/XRT-Alveo-driver-overview/20210428-050424
git checkout 079fb263b22e0d961ac204b3928bdff5d8ebf3d5
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/fpga/xrt/lib/xclbin.c:314:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [usertype] freq @@ got restricted __be16 [usertype] @@
drivers/fpga/xrt/lib/xclbin.c:314:22: sparse: expected unsigned short [usertype] freq
drivers/fpga/xrt/lib/xclbin.c:314:22: sparse: got restricted __be16 [usertype]
--
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/xleaf/vsec.c:270:9: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:273:40: sparse: sparse: cast to restricted __be32
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/xleaf/vsec.c:279:29: sparse: sparse: cast to restricted __be64
--
>> drivers/fpga/xrt/lib/xleaf/icap.c:58:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:58:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:58:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:60:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:60:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:60:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:62:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:62:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:62:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:64:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:64:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:64:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:66:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:66:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:66:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:68:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:68:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:68:9: sparse: got restricted __be32 [usertype]
drivers/fpga/xrt/lib/xleaf/icap.c:70:9: sparse: sparse: incorrect type in initializer (different base types) @@ expected unsigned int @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/lib/xleaf/icap.c:70:9: sparse: expected unsigned int
drivers/fpga/xrt/lib/xleaf/icap.c:70:9: sparse: got restricted __be32 [usertype]
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/xleaf/icap.c:113:25: sparse: sparse: cast to restricted __be32
--
>> drivers/fpga/xrt/lib/xleaf/clock.c:506:31: sparse: sparse: cast to restricted __be16
>> drivers/fpga/xrt/lib/xleaf/clock.c:506:31: sparse: sparse: cast to restricted __be16
>> drivers/fpga/xrt/lib/xleaf/clock.c:506:31: sparse: sparse: cast to restricted __be16
>> drivers/fpga/xrt/lib/xleaf/clock.c:506:31: sparse: sparse: cast to restricted __be16
--
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:195:33: sparse: sparse: cast to restricted __be32
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
>> drivers/fpga/xrt/lib/subdev.c:197:57: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:198:55: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
drivers/fpga/xrt/lib/subdev.c:199:25: sparse: sparse: cast to restricted __be64
--
>> drivers/fpga/xrt/metadata/metadata.c:311:21: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [usertype] val @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/metadata/metadata.c:311:21: sparse: expected unsigned int [usertype] val
drivers/fpga/xrt/metadata/metadata.c:311:21: sparse: got restricted __be32 [usertype]
>> drivers/fpga/xrt/metadata/metadata.c:319:29: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned long long @@ got restricted __be64 [usertype] @@
drivers/fpga/xrt/metadata/metadata.c:319:29: sparse: expected unsigned long long
drivers/fpga/xrt/metadata/metadata.c:319:29: sparse: got restricted __be64 [usertype]
drivers/fpga/xrt/metadata/metadata.c:320:29: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned long long @@ got restricted __be64 [usertype] @@
drivers/fpga/xrt/metadata/metadata.c:320:29: sparse: expected unsigned long long
drivers/fpga/xrt/metadata/metadata.c:320:29: sparse: got restricted __be64 [usertype]
--
>> drivers/fpga/xrt/mgnt/xmgnt-main-region.c:71:30: sparse: sparse: symbol 'xmgnt_bridge_ops' was not declared. Should it be static?
--
>> drivers/fpga/xrt/mgnt/root.c:211:18: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [usertype] vsec_bar @@ got restricted __be32 [usertype] @@
drivers/fpga/xrt/mgnt/root.c:211:18: sparse: expected unsigned int [usertype] vsec_bar
drivers/fpga/xrt/mgnt/root.c:211:18: sparse: got restricted __be32 [usertype]
>> drivers/fpga/xrt/mgnt/root.c:219:18: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned long long [usertype] vsec_off @@ got restricted __be64 [usertype] @@
drivers/fpga/xrt/mgnt/root.c:219:18: sparse: expected unsigned long long [usertype] vsec_off
drivers/fpga/xrt/mgnt/root.c:219:18: sparse: got restricted __be64 [usertype]
--
>> drivers/fpga/xrt/mgnt/xmgnt-main.c:570:56: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const [noderef] __user *from @@ got struct axlf *[addressable] xclbin @@
drivers/fpga/xrt/mgnt/xmgnt-main.c:570:56: sparse: expected void const [noderef] __user *from
drivers/fpga/xrt/mgnt/xmgnt-main.c:570:56: sparse: got struct axlf *[addressable] xclbin
drivers/fpga/xrt/mgnt/xmgnt-main.c:585:48: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const [noderef] __user *from @@ got struct axlf *[addressable] xclbin @@
drivers/fpga/xrt/mgnt/xmgnt-main.c:585:48: sparse: expected void const [noderef] __user *from
drivers/fpga/xrt/mgnt/xmgnt-main.c:585:48: sparse: got struct axlf *[addressable] xclbin
Please review and possibly fold the followup patch.
vim +314 drivers/fpga/xrt/lib/xclbin.c
d174deaba7ea5f Lizhi Hou 2021-04-27 243
d174deaba7ea5f Lizhi Hou 2021-04-27 244 struct xrt_clock_desc {
d174deaba7ea5f Lizhi Hou 2021-04-27 245 char *clock_ep_name;
d174deaba7ea5f Lizhi Hou 2021-04-27 246 u32 clock_xclbin_type;
d174deaba7ea5f Lizhi Hou 2021-04-27 247 char *clkfreq_ep_name;
d174deaba7ea5f Lizhi Hou 2021-04-27 @248 } clock_desc[] = {
d174deaba7ea5f Lizhi Hou 2021-04-27 249 {
d174deaba7ea5f Lizhi Hou 2021-04-27 250 .clock_ep_name = XRT_MD_NODE_CLK_KERNEL1,
d174deaba7ea5f Lizhi Hou 2021-04-27 251 .clock_xclbin_type = CT_DATA,
d174deaba7ea5f Lizhi Hou 2021-04-27 252 .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K1,
d174deaba7ea5f Lizhi Hou 2021-04-27 253 },
d174deaba7ea5f Lizhi Hou 2021-04-27 254 {
d174deaba7ea5f Lizhi Hou 2021-04-27 255 .clock_ep_name = XRT_MD_NODE_CLK_KERNEL2,
d174deaba7ea5f Lizhi Hou 2021-04-27 256 .clock_xclbin_type = CT_KERNEL,
d174deaba7ea5f Lizhi Hou 2021-04-27 257 .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K2,
d174deaba7ea5f Lizhi Hou 2021-04-27 258 },
d174deaba7ea5f Lizhi Hou 2021-04-27 259 {
d174deaba7ea5f Lizhi Hou 2021-04-27 260 .clock_ep_name = XRT_MD_NODE_CLK_KERNEL3,
d174deaba7ea5f Lizhi Hou 2021-04-27 261 .clock_xclbin_type = CT_SYSTEM,
d174deaba7ea5f Lizhi Hou 2021-04-27 262 .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_HBM,
d174deaba7ea5f Lizhi Hou 2021-04-27 263 },
d174deaba7ea5f Lizhi Hou 2021-04-27 264 };
d174deaba7ea5f Lizhi Hou 2021-04-27 265
d174deaba7ea5f Lizhi Hou 2021-04-27 266 const char *xrt_clock_type2epname(enum XCLBIN_CLOCK_TYPE type)
d174deaba7ea5f Lizhi Hou 2021-04-27 267 {
d174deaba7ea5f Lizhi Hou 2021-04-27 268 int i;
d174deaba7ea5f Lizhi Hou 2021-04-27 269
d174deaba7ea5f Lizhi Hou 2021-04-27 270 for (i = 0; i < ARRAY_SIZE(clock_desc); i++) {
d174deaba7ea5f Lizhi Hou 2021-04-27 271 if (clock_desc[i].clock_xclbin_type == type)
d174deaba7ea5f Lizhi Hou 2021-04-27 272 return clock_desc[i].clock_ep_name;
d174deaba7ea5f Lizhi Hou 2021-04-27 273 }
d174deaba7ea5f Lizhi Hou 2021-04-27 274 return NULL;
d174deaba7ea5f Lizhi Hou 2021-04-27 275 }
d174deaba7ea5f Lizhi Hou 2021-04-27 276 EXPORT_SYMBOL_GPL(xrt_clock_type2epname);
d174deaba7ea5f Lizhi Hou 2021-04-27 277
d174deaba7ea5f Lizhi Hou 2021-04-27 278 static const char *clock_type2clkfreq_name(enum XCLBIN_CLOCK_TYPE type)
d174deaba7ea5f Lizhi Hou 2021-04-27 279 {
d174deaba7ea5f Lizhi Hou 2021-04-27 280 int i;
d174deaba7ea5f Lizhi Hou 2021-04-27 281
d174deaba7ea5f Lizhi Hou 2021-04-27 282 for (i = 0; i < ARRAY_SIZE(clock_desc); i++) {
d174deaba7ea5f Lizhi Hou 2021-04-27 283 if (clock_desc[i].clock_xclbin_type == type)
d174deaba7ea5f Lizhi Hou 2021-04-27 284 return clock_desc[i].clkfreq_ep_name;
d174deaba7ea5f Lizhi Hou 2021-04-27 285 }
d174deaba7ea5f Lizhi Hou 2021-04-27 286 return NULL;
d174deaba7ea5f Lizhi Hou 2021-04-27 287 }
d174deaba7ea5f Lizhi Hou 2021-04-27 288
d174deaba7ea5f Lizhi Hou 2021-04-27 289 static int xrt_xclbin_add_clock_metadata(struct device *dev,
d174deaba7ea5f Lizhi Hou 2021-04-27 290 const struct axlf *xclbin,
d174deaba7ea5f Lizhi Hou 2021-04-27 291 char *dtb)
d174deaba7ea5f Lizhi Hou 2021-04-27 292 {
d174deaba7ea5f Lizhi Hou 2021-04-27 293 struct clock_freq_topology *clock_topo;
d174deaba7ea5f Lizhi Hou 2021-04-27 294 u16 freq;
d174deaba7ea5f Lizhi Hou 2021-04-27 295 int rc;
d174deaba7ea5f Lizhi Hou 2021-04-27 296 int i;
d174deaba7ea5f Lizhi Hou 2021-04-27 297
d174deaba7ea5f Lizhi Hou 2021-04-27 298 /* if clock section does not exist, add nothing and return success */
d174deaba7ea5f Lizhi Hou 2021-04-27 299 rc = xrt_xclbin_get_section(dev, xclbin, CLOCK_FREQ_TOPOLOGY,
d174deaba7ea5f Lizhi Hou 2021-04-27 300 (void **)&clock_topo, NULL);
d174deaba7ea5f Lizhi Hou 2021-04-27 301 if (rc == -ENOENT)
d174deaba7ea5f Lizhi Hou 2021-04-27 302 return 0;
d174deaba7ea5f Lizhi Hou 2021-04-27 303 else if (rc)
d174deaba7ea5f Lizhi Hou 2021-04-27 304 return rc;
d174deaba7ea5f Lizhi Hou 2021-04-27 305
d174deaba7ea5f Lizhi Hou 2021-04-27 306 for (i = 0; i < clock_topo->count; i++) {
d174deaba7ea5f Lizhi Hou 2021-04-27 307 u8 type = clock_topo->clock_freq[i].type;
d174deaba7ea5f Lizhi Hou 2021-04-27 308 const char *ep_name = xrt_clock_type2epname(type);
d174deaba7ea5f Lizhi Hou 2021-04-27 309 const char *counter_name = clock_type2clkfreq_name(type);
d174deaba7ea5f Lizhi Hou 2021-04-27 310
d174deaba7ea5f Lizhi Hou 2021-04-27 311 if (!ep_name || !counter_name)
d174deaba7ea5f Lizhi Hou 2021-04-27 312 continue;
d174deaba7ea5f Lizhi Hou 2021-04-27 313
d174deaba7ea5f Lizhi Hou 2021-04-27 @314 freq = cpu_to_be16(clock_topo->clock_freq[i].freq_MHZ);
d174deaba7ea5f Lizhi Hou 2021-04-27 315 rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_FREQ,
d174deaba7ea5f Lizhi Hou 2021-04-27 316 &freq, sizeof(freq));
d174deaba7ea5f Lizhi Hou 2021-04-27 317 if (rc)
d174deaba7ea5f Lizhi Hou 2021-04-27 318 break;
d174deaba7ea5f Lizhi Hou 2021-04-27 319
d174deaba7ea5f Lizhi Hou 2021-04-27 320 rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_CNT,
d174deaba7ea5f Lizhi Hou 2021-04-27 321 counter_name, strlen(counter_name) + 1);
d174deaba7ea5f Lizhi Hou 2021-04-27 322 if (rc)
d174deaba7ea5f Lizhi Hou 2021-04-27 323 break;
d174deaba7ea5f Lizhi Hou 2021-04-27 324 }
d174deaba7ea5f Lizhi Hou 2021-04-27 325
d174deaba7ea5f Lizhi Hou 2021-04-27 326 vfree(clock_topo);
d174deaba7ea5f Lizhi Hou 2021-04-27 327
d174deaba7ea5f Lizhi Hou 2021-04-27 328 return rc;
d174deaba7ea5f Lizhi Hou 2021-04-27 329 }
d174deaba7ea5f Lizhi Hou 2021-04-27 330
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 4/27/21 1:54 PM, Lizhi Hou wrote: > Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com> > --- > MAINTAINERS | 11 +++++++++++ > drivers/Makefile | 1 + > drivers/fpga/Kconfig | 2 ++ > drivers/fpga/Makefile | 5 +++++ > drivers/fpga/xrt/Kconfig | 8 ++++++++ > drivers/fpga/xrt/lib/Kconfig | 17 +++++++++++++++++ > drivers/fpga/xrt/lib/Makefile | 30 ++++++++++++++++++++++++++++++ > drivers/fpga/xrt/metadata/Kconfig | 12 ++++++++++++ > drivers/fpga/xrt/metadata/Makefile | 16 ++++++++++++++++ > drivers/fpga/xrt/mgnt/Kconfig | 15 +++++++++++++++ > drivers/fpga/xrt/mgnt/Makefile | 19 +++++++++++++++++++ > 11 files changed, 136 insertions(+) > create mode 100644 drivers/fpga/xrt/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Makefile > create mode 100644 drivers/fpga/xrt/metadata/Kconfig > create mode 100644 drivers/fpga/xrt/metadata/Makefile > create mode 100644 drivers/fpga/xrt/mgnt/Kconfig > create mode 100644 drivers/fpga/xrt/mgnt/Makefile > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9450e052f1b1..89abe140041b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -7016,6 +7016,17 @@ F: Documentation/fpga/ > F: drivers/fpga/ > F: include/linux/fpga/ > > +FPGA XRT DRIVERS > +M: Lizhi Hou <lizhi.hou@xilinx.com> > +R: Max Zhen <max.zhen@xilinx.com> > +R: Sonal Santan <sonal.santan@xilinx.com> > +L: linux-fpga@vger.kernel.org > +S: Supported ok > +W: https://github.com/Xilinx/XRT > +F: Documentation/fpga/xrt.rst > +F: drivers/fpga/xrt/ > +F: include/uapi/linux/xrt/ > + > FPU EMULATOR > M: Bill Metzenthen <billm@melbpc.org.au> > S: Maintained > diff --git a/drivers/Makefile b/drivers/Makefile > index 6fba7daba591..dbb3b727fc7a 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -179,6 +179,7 @@ obj-$(CONFIG_STM) += hwtracing/stm/ > obj-$(CONFIG_ANDROID) += android/ > obj-$(CONFIG_NVMEM) += nvmem/ > obj-$(CONFIG_FPGA) += fpga/ > +obj-$(CONFIG_FPGA_XRT_METADATA) += fpga/ > obj-$(CONFIG_FSI) += fsi/ > obj-$(CONFIG_TEE) += tee/ > obj-$(CONFIG_MULTIPLEXER) += mux/ > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 5ff9438b7b46..01410ff000b9 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -227,4 +227,6 @@ config FPGA_MGR_ZYNQMP_FPGA > to configure the programmable logic(PL) through PS > on ZynqMP SoC. > > +source "drivers/fpga/xrt/Kconfig" > + > endif # FPGA > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index 18dc9885883a..a1cad7f7af09 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -48,3 +48,8 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o > > # Drivers for FPGAs which implement DFL > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o > + > +# XRT drivers for Alveo > +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt/metadata/ > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ > +obj-$(CONFIG_FPGA_XRT_XMGNT) += xrt/mgnt/ > diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig > new file mode 100644 > index 000000000000..2424f89e6e03 > --- /dev/null > +++ b/drivers/fpga/xrt/Kconfig > @@ -0,0 +1,8 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Xilinx Alveo FPGA device configuration > +# > + > +source "drivers/fpga/xrt/metadata/Kconfig" > +source "drivers/fpga/xrt/lib/Kconfig" > +source "drivers/fpga/xrt/mgnt/Kconfig" > diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig > new file mode 100644 > index 000000000000..935369fad570 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/Kconfig > @@ -0,0 +1,17 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# XRT Alveo FPGA device configuration > +# > + > +config FPGA_XRT_LIB > + tristate "XRT Alveo Driver Library" > + depends on HWMON && PCI && HAS_IOMEM > + select FPGA_XRT_METADATA > + select REGMAP_MMIO > + help > + Select this option to enable Xilinx XRT Alveo driver library. This > + library is core infrastructure of XRT Alveo FPGA drivers which > + provides functions for working with device nodes, iteration and > + lookup of platform devices, common interfaces for platform devices, > + plumbing of function call and ioctls between platform devices and > + parent partitions. ok > diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile > new file mode 100644 > index 000000000000..58563416efbf > --- /dev/null > +++ b/drivers/fpga/xrt/lib/Makefile > @@ -0,0 +1,30 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o > + > +xrt-lib-objs := \ > + lib-drv.o \ > + xroot.o \ > + xclbin.o \ > + subdev.o \ > + cdev.o \ > + group.o \ > + xleaf/vsec.o \ > + xleaf/axigate.o \ > + xleaf/devctl.o \ > + xleaf/icap.o \ > + xleaf/clock.o \ > + xleaf/clkfreq.o \ > + xleaf/ucs.o \ > + xleaf/ddr_calibration.o > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH) > diff --git a/drivers/fpga/xrt/metadata/Kconfig b/drivers/fpga/xrt/metadata/Kconfig > new file mode 100644 > index 000000000000..129adda47e94 > --- /dev/null > +++ b/drivers/fpga/xrt/metadata/Kconfig > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# XRT Alveo FPGA device configuration > +# > + > +config FPGA_XRT_METADATA > + bool "XRT Alveo Driver Metadata Parser" > + select LIBFDT > + help > + This option provides helper functions to parse Xilinx Alveo FPGA > + firmware metadata. The metadata is in device tree format and the > + XRT driver uses it to discover the HW subsystems behind PCIe BAR. ok > diff --git a/drivers/fpga/xrt/metadata/Makefile b/drivers/fpga/xrt/metadata/Makefile > new file mode 100644 > index 000000000000..14f65ef1595c > --- /dev/null > +++ b/drivers/fpga/xrt/metadata/Makefile > @@ -0,0 +1,16 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt-md.o > + > +xrt-md-objs := metadata.o > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH) > diff --git a/drivers/fpga/xrt/mgnt/Kconfig b/drivers/fpga/xrt/mgnt/Kconfig > new file mode 100644 > index 000000000000..b43242c14757 > --- /dev/null > +++ b/drivers/fpga/xrt/mgnt/Kconfig > @@ -0,0 +1,15 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Xilinx XRT FPGA device configuration > +# > + > +config FPGA_XRT_XMGNT > + tristate "Xilinx Alveo Management Driver" > + depends on FPGA_XRT_LIB > + select FPGA_XRT_METADATA > + select FPGA_BRIDGE > + select FPGA_REGION > + help > + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. > + This driver provides interfaces for userspace application to access > + Alveo FPGA device. ok good enough for now. Reviewed-by: Tom Rix <trix@redhat.com> > diff --git a/drivers/fpga/xrt/mgnt/Makefile b/drivers/fpga/xrt/mgnt/Makefile > new file mode 100644 > index 000000000000..b71d2ff0aa94 > --- /dev/null > +++ b/drivers/fpga/xrt/mgnt/Makefile > @@ -0,0 +1,19 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_XMGNT) += xrt-mgnt.o > + > +xrt-mgnt-objs := root.o \ > + xmgnt-main.o \ > + xrt-mgr.o \ > + xmgnt-main-region.o > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH)
diff --git a/MAINTAINERS b/MAINTAINERS index 9450e052f1b1..89abe140041b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7016,6 +7016,17 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +FPGA XRT DRIVERS +M: Lizhi Hou <lizhi.hou@xilinx.com> +R: Max Zhen <max.zhen@xilinx.com> +R: Sonal Santan <sonal.santan@xilinx.com> +L: linux-fpga@vger.kernel.org +S: Supported +W: https://github.com/Xilinx/XRT +F: Documentation/fpga/xrt.rst +F: drivers/fpga/xrt/ +F: include/uapi/linux/xrt/ + FPU EMULATOR M: Bill Metzenthen <billm@melbpc.org.au> S: Maintained diff --git a/drivers/Makefile b/drivers/Makefile index 6fba7daba591..dbb3b727fc7a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -179,6 +179,7 @@ obj-$(CONFIG_STM) += hwtracing/stm/ obj-$(CONFIG_ANDROID) += android/ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ +obj-$(CONFIG_FPGA_XRT_METADATA) += fpga/ obj-$(CONFIG_FSI) += fsi/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 5ff9438b7b46..01410ff000b9 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -227,4 +227,6 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +source "drivers/fpga/xrt/Kconfig" + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 18dc9885883a..a1cad7f7af09 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -48,3 +48,8 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o + +# XRT drivers for Alveo +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt/metadata/ +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ +obj-$(CONFIG_FPGA_XRT_XMGNT) += xrt/mgnt/ diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig new file mode 100644 index 000000000000..2424f89e6e03 --- /dev/null +++ b/drivers/fpga/xrt/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx Alveo FPGA device configuration +# + +source "drivers/fpga/xrt/metadata/Kconfig" +source "drivers/fpga/xrt/lib/Kconfig" +source "drivers/fpga/xrt/mgnt/Kconfig" diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig new file mode 100644 index 000000000000..935369fad570 --- /dev/null +++ b/drivers/fpga/xrt/lib/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# XRT Alveo FPGA device configuration +# + +config FPGA_XRT_LIB + tristate "XRT Alveo Driver Library" + depends on HWMON && PCI && HAS_IOMEM + select FPGA_XRT_METADATA + select REGMAP_MMIO + help + Select this option to enable Xilinx XRT Alveo driver library. This + library is core infrastructure of XRT Alveo FPGA drivers which + provides functions for working with device nodes, iteration and + lookup of platform devices, common interfaces for platform devices, + plumbing of function call and ioctls between platform devices and + parent partitions. diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile new file mode 100644 index 000000000000..58563416efbf --- /dev/null +++ b/drivers/fpga/xrt/lib/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt + +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o + +xrt-lib-objs := \ + lib-drv.o \ + xroot.o \ + xclbin.o \ + subdev.o \ + cdev.o \ + group.o \ + xleaf/vsec.o \ + xleaf/axigate.o \ + xleaf/devctl.o \ + xleaf/icap.o \ + xleaf/clock.o \ + xleaf/clkfreq.o \ + xleaf/ucs.o \ + xleaf/ddr_calibration.o + +ccflags-y := -I$(FULL_XRT_PATH)/include \ + -I$(FULL_DTC_PATH) diff --git a/drivers/fpga/xrt/metadata/Kconfig b/drivers/fpga/xrt/metadata/Kconfig new file mode 100644 index 000000000000..129adda47e94 --- /dev/null +++ b/drivers/fpga/xrt/metadata/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# XRT Alveo FPGA device configuration +# + +config FPGA_XRT_METADATA + bool "XRT Alveo Driver Metadata Parser" + select LIBFDT + help + This option provides helper functions to parse Xilinx Alveo FPGA + firmware metadata. The metadata is in device tree format and the + XRT driver uses it to discover the HW subsystems behind PCIe BAR. diff --git a/drivers/fpga/xrt/metadata/Makefile b/drivers/fpga/xrt/metadata/Makefile new file mode 100644 index 000000000000..14f65ef1595c --- /dev/null +++ b/drivers/fpga/xrt/metadata/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt + +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt-md.o + +xrt-md-objs := metadata.o + +ccflags-y := -I$(FULL_XRT_PATH)/include \ + -I$(FULL_DTC_PATH) diff --git a/drivers/fpga/xrt/mgnt/Kconfig b/drivers/fpga/xrt/mgnt/Kconfig new file mode 100644 index 000000000000..b43242c14757 --- /dev/null +++ b/drivers/fpga/xrt/mgnt/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx XRT FPGA device configuration +# + +config FPGA_XRT_XMGNT + tristate "Xilinx Alveo Management Driver" + depends on FPGA_XRT_LIB + select FPGA_XRT_METADATA + select FPGA_BRIDGE + select FPGA_REGION + help + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. + This driver provides interfaces for userspace application to access + Alveo FPGA device. diff --git a/drivers/fpga/xrt/mgnt/Makefile b/drivers/fpga/xrt/mgnt/Makefile new file mode 100644 index 000000000000..b71d2ff0aa94 --- /dev/null +++ b/drivers/fpga/xrt/mgnt/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt + +obj-$(CONFIG_FPGA_XRT_XMGNT) += xrt-mgnt.o + +xrt-mgnt-objs := root.o \ + xmgnt-main.o \ + xrt-mgr.o \ + xmgnt-main-region.o + +ccflags-y := -I$(FULL_XRT_PATH)/include \ + -I$(FULL_DTC_PATH)