From patchwork Fri Mar 11 02:11:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12777297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC0A6C433EF for ; Fri, 11 Mar 2022 02:16:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244318AbiCKCPp (ORCPT ); Thu, 10 Mar 2022 21:15:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233354AbiCKCPo (ORCPT ); Thu, 10 Mar 2022 21:15:44 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC0C8C5DA9; Thu, 10 Mar 2022 18:14:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646964883; x=1678500883; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Dv5GNx9VK3y1DpDwUXAucqtut9NvxauOUvgUnuU3e1w=; b=EYtDVx1lbhYHY6uz750EBobkU1fo0j6iwMG8FC4w+tHDrVUR2nRfnxW/ XOMacHwf62YV2drKae9vwIeINwbe2H76CZiA3QDMQBkG6oj4XrZEPGWSV 7VtkYVmOf0Wy/MZglERq4dbpQaPmZ7BzuP1XjhTsr25jHcbGgG8ZfwI2u 0Iq3z5xdHkwH2ub6QxWpHMMJRjoTXP7kmetM7tRwVDD5kzEA0F1+EdEdi JrIEAvC5PcTew/ZhLLu70POxb+ezHxl7mBRylD9QUZeqLqEORsy8MakPL gaqQ6L07FM+MT71sES3aHL0kDv9cYPJ+nbHN8NUKF+wQSA76vHILgnxj8 A==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="255667100" X-IronPort-AV: E=Sophos;i="5.90,172,1643702400"; d="scan'208";a="255667100" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 18:14:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,172,1643702400"; d="scan'208";a="548318297" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga007.fm.intel.com with ESMTP; 10 Mar 2022 18:14:38 -0800 From: Tianfei Zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: corbet@lwn.net, Tianfei Zhang Subject: [PATCH v3] fpga: dfl: check feature type before parse irq info Date: Thu, 10 Mar 2022 21:11:21 -0500 Message-Id: <20220311021121.1504442-1-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The feature ID of "Port User Interrupt" and the "PMCI Subsystem" are identical, 0x12, but one is for FME, other is for Port. It should check the feature type While parsing the irq info in parse_feature_irqs(). --- v3: Remove "Fixes" in commit log with Hao's comment, this is a extension not a bug fix. v2: add DFL Feature ID Registry in documentation. Signed-off-by: Tianfei Zhang --- Documentation/fpga/dfl.rst | 11 +++++++++++ drivers/fpga/dfl.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..14f342bb85e4 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,17 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. +The definition of Feature Type and Feature ID can be found: + +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst + +If you want to add a new feature ID for FPGA DFL feature device, we recommend that +use a pull request to reserve a feature ID for DFL. Here is the DFL Feature ID +Registry: + +https://github.com/OPAE/linux-dfl-feature-id + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 599bb21d86af..6bff39ff21a0 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + enum dfl_id_type type; int virq; u64 v; + type = feature_dev_id_type(binfo->feature_dev); + /* * Ideally DFL framework should only read info from DFL header, but * current version DFL only provides mmio resources information for @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, * code will be added. But in order to be compatible to old version * DFL, the driver may still fall back to these quirks. */ - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); - break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); - break; - case FME_FEATURE_ID_GLOBAL_ERR: - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - break; + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + if (fid == FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + } } if (!inr) {