diff mbox series

[v7,2/2] Documentation: fpga: dfl: add link address of feature id table

Message ID 20220419032942.427429-3-tianfei.zhang@intel.com (mailing list archive)
State New
Headers show
Series check feature type for DFL irq parsing | expand

Commit Message

Tianfei Zhang April 19, 2022, 3:29 a.m. UTC
From: Tianfei zhang <tianfei.zhang@intel.com>

This patch adds the link address of feature id table in documentation.

Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
---
v7:
  - change the title and git commit message.
  - add Reviewed by from Matthew Gerlach.
v6: fix documentation from Hao's comment.
v5: fix documentation from Matthew's comment.
---
 Documentation/fpga/dfl.rst | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Moritz Fischer April 21, 2022, 2:47 p.m. UTC | #1
On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> From: Tianfei zhang <tianfei.zhang@intel.com>
> 
> This patch adds the link address of feature id table in documentation.
> 
> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v7:
>   - change the title and git commit message.
>   - add Reviewed by from Matthew Gerlach.
> v6: fix documentation from Hao's comment.
> v5: fix documentation from Matthew's comment.
> ---
>  Documentation/fpga/dfl.rst | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> index ef9eec71f6f3..15b670926084 100644
> --- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
>  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
>  could be a reference.
>  
> +Please refer to below link to existing feature id table and guide for new feature
> +ids application.
> +https://github.com/OPAE/dfl-feature-id
> +
> +
>  Location of DFLs on a PCI Device
>  ================================
>  The original method for finding a DFL on a PCI device assumed the start of the
> -- 
> 2.26.2
>
Xu Yilun April 25, 2022, 7:23 a.m. UTC | #2
On Thu, Apr 21, 2022 at 07:47:18AM -0700, Moritz Fischer wrote:
> On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> > From: Tianfei zhang <tianfei.zhang@intel.com>
> > 
> > This patch adds the link address of feature id table in documentation.
> > 
> > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> Acked-by: Moritz Fischer <mdf@kernel.org>

Acked-by: Xu Yilun <yilun.xu@intel.com>

> > ---
> > v7:
> >   - change the title and git commit message.
> >   - add Reviewed by from Matthew Gerlach.
> > v6: fix documentation from Hao's comment.
> > v5: fix documentation from Matthew's comment.
> > ---
> >  Documentation/fpga/dfl.rst | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> > index ef9eec71f6f3..15b670926084 100644
> > --- a/Documentation/fpga/dfl.rst
> > +++ b/Documentation/fpga/dfl.rst
> > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
> >  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
> >  could be a reference.
> >  
> > +Please refer to below link to existing feature id table and guide for new feature
> > +ids application.
> > +https://github.com/OPAE/dfl-feature-id
> > +
> > +
> >  Location of DFLs on a PCI Device
> >  ================================
> >  The original method for finding a DFL on a PCI device assumed the start of the
> > -- 
> > 2.26.2
> >
Wu, Hao April 26, 2022, 2:15 a.m. UTC | #3
> -----Original Message-----
> From: Xu, Yilun <yilun.xu@intel.com>
> Sent: Monday, April 25, 2022 3:23 PM
> To: Moritz Fischer <mdf@kernel.org>
> Cc: Zhang, Tianfei <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com>;
> trix@redhat.com; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.org;
> corbet@lwn.net; Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Subject: Re: [PATCH v7 2/2] Documentation: fpga: dfl: add link address of
> feature id table
> 
> On Thu, Apr 21, 2022 at 07:47:18AM -0700, Moritz Fischer wrote:
> > On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> > > From: Tianfei zhang <tianfei.zhang@intel.com>
> > >
> > > This patch adds the link address of feature id table in documentation.
> > >
> > > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> > Acked-by: Moritz Fischer <mdf@kernel.org>
> 
> Acked-by: Xu Yilun <yilun.xu@intel.com>
> 

Acked-by: Wu Hao <hao.wu@intel.com>

> > > ---
> > > v7:
> > >   - change the title and git commit message.
> > >   - add Reviewed by from Matthew Gerlach.
> > > v6: fix documentation from Hao's comment.
> > > v5: fix documentation from Matthew's comment.
> > > ---
> > >  Documentation/fpga/dfl.rst | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> > > index ef9eec71f6f3..15b670926084 100644
> > > --- a/Documentation/fpga/dfl.rst
> > > +++ b/Documentation/fpga/dfl.rst
> > > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature
> driver with matched feature id.
> > >  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-
> pr.c)
> > >  could be a reference.
> > >
> > > +Please refer to below link to existing feature id table and guide for new
> feature
> > > +ids application.
> > > +https://github.com/OPAE/dfl-feature-id
> > > +
> > > +
> > >  Location of DFLs on a PCI Device
> > >  ================================
> > >  The original method for finding a DFL on a PCI device assumed the start of
> the
> > > --
> > > 2.26.2
> > >
diff mbox series

Patch

diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index ef9eec71f6f3..15b670926084 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -502,6 +502,11 @@  Developer only needs to provide a sub feature driver with matched feature id.
 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
 could be a reference.
 
+Please refer to below link to existing feature id table and guide for new feature
+ids application.
+https://github.com/OPAE/dfl-feature-id
+
+
 Location of DFLs on a PCI Device
 ================================
 The original method for finding a DFL on a PCI device assumed the start of the