diff mbox series

[v3] fpga: dfl: Allow Port to be linked to FME's DFL

Message ID 20220426014907.570292-1-tianfei.zhang@intel.com (mailing list archive)
State New
Headers show
Series [v3] fpga: dfl: Allow Port to be linked to FME's DFL | expand

Commit Message

Tianfei Zhang April 26, 2022, 1:49 a.m. UTC
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not
connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device),
PORT DFLs are connected to FME DFL directly, so we don't need to search
PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7
(FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that
port. If BAR value is invalid, return -EINVAL.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
v3: remove dev_dbg and use goto instead of break.
v2: return -EINVAL if bar number invalid.
---
 drivers/fpga/dfl-pci.c | 10 ++++++++++
 drivers/fpga/dfl.h     |  1 +
 2 files changed, 11 insertions(+)

Comments

Wu, Hao April 26, 2022, 2:11 a.m. UTC | #1
> -----Original Message-----
> From: Zhang, Tianfei <tianfei.zhang@intel.com>
> Sent: Tuesday, April 26, 2022 9:49 AM
> To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, Yilun
> <yilun.xu@intel.com>; linux-fpga@vger.kernel.org
> Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>; Zhang, Tianfei
> <tianfei.zhang@intel.com>
> Subject: [PATCH v3] fpga: dfl: Allow Port to be linked to FME's DFL
> 
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not
> connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device),
> PORT DFLs are connected to FME DFL directly, so we don't need to search
> PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7
> (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that
> port. If BAR value is invalid, return -EINVAL.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---
> v3: remove dev_dbg and use goto instead of break.
> v2: return -EINVAL if bar number invalid.
> ---
>  drivers/fpga/dfl-pci.c | 10 ++++++++++
>  drivers/fpga/dfl.h     |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> index 86ed9e4223d3..dac45f96c326 100644
> --- a/drivers/fpga/dfl-pci.c
> +++ b/drivers/fpga/dfl-pci.c
> @@ -263,6 +263,15 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
>  			 */
>  			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
>  			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> +			if (bar == FME_PORT_OFST_BAR_SKIP) {
> +				continue;
> +			} else if (bar >= PCI_STD_NUM_BARS) {
> +				dev_err(&pcidev->dev, "bad BAR %d for
> port %d\n",
> +					bar, i);
> +				ret = -EINVAL;
> +				goto unmap_exit;

will break work here?

> +			}
> +
>  			start = pci_resource_start(pcidev, bar) + offset;
>  			len = pci_resource_len(pcidev, bar) - offset;
> 
> @@ -277,6 +286,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
>  		ret = -ENODEV;
>  	}
> 
> +unmap_exit:
>  	/* release I/O mappings for next step enumeration */
>  	pcim_iounmap_regions(pcidev, BIT(0));
> 
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 53572c7aced0..e0f0abfbeb8c 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -91,6 +91,7 @@
>  #define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
>  #define FME_HDR_BITSTREAM_ID	0x60
>  #define FME_HDR_BITSTREAM_MD	0x68
> +#define FME_PORT_OFST_BAR_SKIP	7

Move this line under FME_HDR_PORT_OFST(n), 
other place looks good to me.


> 
>  /* FME Fab Capability Register Bitfield */
>  #define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric
> version ID */
> --
> 2.26.2
Tianfei Zhang April 26, 2022, 2:17 a.m. UTC | #2
> -----Original Message-----
> From: Wu, Hao <hao.wu@intel.com>
> Sent: Tuesday, April 26, 2022 10:12 AM
> To: Zhang, Tianfei <tianfei.zhang@intel.com>; trix@redhat.com;
> mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org
> Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Subject: RE: [PATCH v3] fpga: dfl: Allow Port to be linked to FME's DFL
> 
> > -----Original Message-----
> > From: Zhang, Tianfei <tianfei.zhang@intel.com>
> > Sent: Tuesday, April 26, 2022 9:49 AM
> > To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu,
> > Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org
> > Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>; Zhang, Tianfei
> > <tianfei.zhang@intel.com>
> > Subject: [PATCH v3] fpga: dfl: Allow Port to be linked to FME's DFL
> >
> > From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> >
> > Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are
> > not connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack
> > device), PORT DFLs are connected to FME DFL directly, so we don't need
> > to search PORT DFLs via PORTn_OFFSET again. If BAR value of
> > PORTn_OFFSET is 0x7
> > (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for
> > that port. If BAR value is invalid, return -EINVAL.
> >
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> > ---
> > v3: remove dev_dbg and use goto instead of break.
> > v2: return -EINVAL if bar number invalid.
> > ---
> >  drivers/fpga/dfl-pci.c | 10 ++++++++++
> >  drivers/fpga/dfl.h     |  1 +
> >  2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index
> > 86ed9e4223d3..dac45f96c326 100644
> > --- a/drivers/fpga/dfl-pci.c
> > +++ b/drivers/fpga/dfl-pci.c
> > @@ -263,6 +263,15 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
> >  			 */
> >  			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
> >  			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> > +			if (bar == FME_PORT_OFST_BAR_SKIP) {
> > +				continue;
> > +			} else if (bar >= PCI_STD_NUM_BARS) {
> > +				dev_err(&pcidev->dev, "bad BAR %d for
> > port %d\n",
> > +					bar, i);
> > +				ret = -EINVAL;
> > +				goto unmap_exit;
> 
> will break work here?
Yes, I think if Bar >= PCI_STD_NUM_BARS, this should be DFL hardware issue.

> 
> > +			}
> > +
> >  			start = pci_resource_start(pcidev, bar) + offset;
> >  			len = pci_resource_len(pcidev, bar) - offset;
> >
> > @@ -277,6 +286,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
> >  		ret = -ENODEV;
> >  	}
> >
> > +unmap_exit:
> >  	/* release I/O mappings for next step enumeration */
> >  	pcim_iounmap_regions(pcidev, BIT(0));
> >
> > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index
> > 53572c7aced0..e0f0abfbeb8c 100644
> > --- a/drivers/fpga/dfl.h
> > +++ b/drivers/fpga/dfl.h
> > @@ -91,6 +91,7 @@
> >  #define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
> >  #define FME_HDR_BITSTREAM_ID	0x60
> >  #define FME_HDR_BITSTREAM_MD	0x68
> > +#define FME_PORT_OFST_BAR_SKIP	7
> 
> Move this line under FME_HDR_PORT_OFST(n), other place looks good to me.
Ok, I agree, I will fix it.
> 
> 
> >
> >  /* FME Fab Capability Register Bitfield */
> >  #define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric
> > version ID */
> > --
> > 2.26.2
diff mbox series

Patch

diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index 86ed9e4223d3..dac45f96c326 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -263,6 +263,15 @@  static int find_dfls_by_default(struct pci_dev *pcidev,
 			 */
 			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
 			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
+			if (bar == FME_PORT_OFST_BAR_SKIP) {
+				continue;
+			} else if (bar >= PCI_STD_NUM_BARS) {
+				dev_err(&pcidev->dev, "bad BAR %d for port %d\n",
+					bar, i);
+				ret = -EINVAL;
+				goto unmap_exit;
+			}
+
 			start = pci_resource_start(pcidev, bar) + offset;
 			len = pci_resource_len(pcidev, bar) - offset;
 
@@ -277,6 +286,7 @@  static int find_dfls_by_default(struct pci_dev *pcidev,
 		ret = -ENODEV;
 	}
 
+unmap_exit:
 	/* release I/O mappings for next step enumeration */
 	pcim_iounmap_regions(pcidev, BIT(0));
 
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 53572c7aced0..e0f0abfbeb8c 100644
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -91,6 +91,7 @@ 
 #define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
 #define FME_HDR_BITSTREAM_ID	0x60
 #define FME_HDR_BITSTREAM_MD	0x68
+#define FME_PORT_OFST_BAR_SKIP	7
 
 /* FME Fab Capability Register Bitfield */
 #define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */