diff mbox series

[next] fpga: fpga-mgr: Fix spelling mistake "bitsream" -> "bitstream"

Message ID 20220624081409.14760-1-colin.i.king@gmail.com (mailing list archive)
State New
Headers show
Series [next] fpga: fpga-mgr: Fix spelling mistake "bitsream" -> "bitstream" | expand

Commit Message

Colin Ian King June 24, 2022, 8:14 a.m. UTC
There is an spelling mistake in a dev_err message. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
---
 drivers/fpga/fpga-mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Xu Yilun June 29, 2022, 7:31 a.m. UTC | #1
On Fri, Jun 24, 2022 at 09:14:09AM +0100, Colin Ian King wrote:
> There is an spelling mistake in a dev_err message. Fix it.
> 
> Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
> ---
>  drivers/fpga/fpga-mgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
> index a0fa0a2cb8af..8efa67620e21 100644
> --- a/drivers/fpga/fpga-mgr.c
> +++ b/drivers/fpga/fpga-mgr.c
> @@ -158,7 +158,7 @@ static int fpga_mgr_parse_header_mapped(struct fpga_manager *mgr,
>  	ret = fpga_mgr_parse_header(mgr, info, buf, count);
>  
>  	if (info->header_size + info->data_size > count) {
> -		dev_err(&mgr->dev, "Bitsream data outruns FPGA image\n");
> +		dev_err(&mgr->dev, "Bitstream data outruns FPGA image\n");
>  		ret = -EINVAL;
>  	}

Adds the Fixes tag

  Fixes: 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in image buffer")

and applied to for-next

Thanks,
Yilun

>  
> -- 
> 2.35.3
diff mbox series

Patch

diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index a0fa0a2cb8af..8efa67620e21 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -158,7 +158,7 @@  static int fpga_mgr_parse_header_mapped(struct fpga_manager *mgr,
 	ret = fpga_mgr_parse_header(mgr, info, buf, count);
 
 	if (info->header_size + info->data_size > count) {
-		dev_err(&mgr->dev, "Bitsream data outruns FPGA image\n");
+		dev_err(&mgr->dev, "Bitstream data outruns FPGA image\n");
 		ret = -EINVAL;
 	}