diff mbox series

[RFC,v2] scsi: ufs-mediatek: add inline encryption support

Message ID 20200304022101.14165-1-stanley.chu@mediatek.com
State Superseded
Headers show
Series [RFC,v2] scsi: ufs-mediatek: add inline encryption support | expand

Commit Message

Stanley Chu March 4, 2020, 2:21 a.m. UTC
Add inline encryption support to ufs-mediatek.

The standards-compliant parts, such as querying the crypto capabilities
and enabling crypto for individual UFS requests, are already handled by
ufshcd-crypto.c, which itself is wired into the blk-crypto framework.

However MediaTek UFS host requires a vendor-specific hce_enable operation
to allow crypto-related registers being accessed normally in kernel.
After this step, MediaTek UFS host can work as standard-compliant host
for inline-encryption related functions.

This patch is rebased to below repo and tag:
	Repo: https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git
	Tag: inline-encryption-v7

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
 drivers/scsi/ufs/ufs-mediatek.c | 27 ++++++++++++++++++++++++++-
 drivers/scsi/ufs/ufs-mediatek.h |  1 +
 2 files changed, 27 insertions(+), 1 deletion(-)

Comments

Eric Biggers July 10, 2020, 6:39 a.m. UTC | #1
Hi Stanley,

On Wed, Mar 04, 2020 at 10:21:02AM +0800, Stanley Chu wrote:
> Add inline encryption support to ufs-mediatek.
> 
> The standards-compliant parts, such as querying the crypto capabilities
> and enabling crypto for individual UFS requests, are already handled by
> ufshcd-crypto.c, which itself is wired into the blk-crypto framework.
> 
> However MediaTek UFS host requires a vendor-specific hce_enable operation
> to allow crypto-related registers being accessed normally in kernel.
> After this step, MediaTek UFS host can work as standard-compliant host
> for inline-encryption related functions.
> 
> This patch is rebased to below repo and tag:
> 	Repo: https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git
> 	Tag: inline-encryption-v7
> 
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
>  drivers/scsi/ufs/ufs-mediatek.c | 27 ++++++++++++++++++++++++++-
>  drivers/scsi/ufs/ufs-mediatek.h |  1 +
>  2 files changed, 27 insertions(+), 1 deletion(-)

Now that the ufshcd-crypto patches this depends on are in 5.9/scsi-queue, could
you retest and resend this patch?  It would be nice to have 5.9 support some
real hardware already.  (I'm going to resend my patchset for ufs-qcom too.)

- Eric
Stanley Chu July 12, 2020, 12:34 a.m. UTC | #2
Hi Eric,

On Thu, 2020-07-09 at 23:39 -0700, Eric Biggers wrote:
> Hi Stanley,
> 
> On Wed, Mar 04, 2020 at 10:21:02AM +0800, Stanley Chu wrote:
> > Add inline encryption support to ufs-mediatek.
> > 
> > The standards-compliant parts, such as querying the crypto capabilities
> > and enabling crypto for individual UFS requests, are already handled by
> > ufshcd-crypto.c, which itself is wired into the blk-crypto framework.
> > 
> > However MediaTek UFS host requires a vendor-specific hce_enable operation
> > to allow crypto-related registers being accessed normally in kernel.
> > After this step, MediaTek UFS host can work as standard-compliant host
> > for inline-encryption related functions.
> > 
> > This patch is rebased to below repo and tag:
> > 	Repo: https://urldefense.com/v3/__https://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git__;!!CTRNKA9wMg0ARbw!x8Kltcu8AQhdtlIDXASWjd_ANrBtcYzidIXMsu-fQloEqgvrDDBU9yD9GumtKLIcd_c$ 
> > 	Tag: inline-encryption-v7
> > 
> > Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> > ---
> >  drivers/scsi/ufs/ufs-mediatek.c | 27 ++++++++++++++++++++++++++-
> >  drivers/scsi/ufs/ufs-mediatek.h |  1 +
> >  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> Now that the ufshcd-crypto patches this depends on are in 5.9/scsi-queue, could
> you retest and resend this patch?  It would be nice to have 5.9 support some
> real hardware already.  (I'm going to resend my patchset for ufs-qcom too.)

Sure. Now this patch is resent as v3, please see
https://patchwork.kernel.org/patch/11657987/

Thanks,
Stanley Chu
diff mbox series

Patch

diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index 53eae5fe2ade..12d01fd3d5e1 100644
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -15,6 +15,7 @@ 
 #include <linux/soc/mediatek/mtk_sip_svc.h>
 
 #include "ufshcd.h"
+#include "ufshcd-crypto.h"
 #include "ufshcd-pltfrm.h"
 #include "ufs_quirks.h"
 #include "unipro.h"
@@ -24,6 +25,9 @@ 
 	arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
 		      cmd, val, 0, 0, 0, 0, 0, &(res))
 
+#define ufs_mtk_crypto_ctrl(res, enable) \
+	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, enable, res)
+
 #define ufs_mtk_ref_clk_notify(on, res) \
 	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
 
@@ -66,7 +70,27 @@  static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
 	}
 }
 
-static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
+static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
+{
+	struct arm_smccc_res res;
+
+	ufs_mtk_crypto_ctrl(res, 1);
+	if (res.a0) {
+		dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
+			 __func__, res.a0);
+	}
+}
+
+static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
+				     enum ufs_notify_change_status status)
+{
+	if (status == PRE_CHANGE && ufshcd_hba_is_crypto_supported(hba))
+		ufs_mtk_crypto_enable(hba);
+
+	return 0;
+}
+
+int ufs_mtk_bind_mphy(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 	struct device *dev = hba->dev;
@@ -494,6 +518,7 @@  static struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
 	.name                = "mediatek.ufshci",
 	.init                = ufs_mtk_init,
 	.setup_clocks        = ufs_mtk_setup_clocks,
+	.hce_enable_notify   = ufs_mtk_hce_enable_notify,
 	.link_startup_notify = ufs_mtk_link_startup_notify,
 	.pwr_change_notify   = ufs_mtk_pwr_change_notify,
 	.apply_dev_quirks    = ufs_mtk_apply_dev_quirks,
diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
index fccdd979d6fb..5ebaa59898bf 100644
--- a/drivers/scsi/ufs/ufs-mediatek.h
+++ b/drivers/scsi/ufs/ufs-mediatek.h
@@ -58,6 +58,7 @@ 
  */
 #define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
+#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
 
 /*