Message ID | 20241213041958.202565-6-ebiggers@kernel.org (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Support for hardware-wrapped inline encryption keys | expand |
On Fri, 13 Dec 2024 at 05:20, Eric Biggers <ebiggers@kernel.org> wrote: > > From: Eric Biggers <ebiggers@google.com> > > Commit c7eed31e235c ("mmc: sdhci-msm: Switch to the new ICE API") > introduced an incorrect check of the algorithm ID into the key eviction > path, and thus qcom_ice_evict_key() is no longer ever called. Fix it. > > Fixes: c7eed31e235c ("mmc: sdhci-msm: Switch to the new ICE API") > Cc: stable@vger.kernel.org > Cc: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Eric Biggers <ebiggers@google.com> Applied for fixes, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-msm.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index e00208535bd1..319f0ebbe652 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -1865,24 +1865,24 @@ static int sdhci_msm_program_key(struct cqhci_host *cq_host, > struct sdhci_host *host = mmc_priv(cq_host->mmc); > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > union cqhci_crypto_cap_entry cap; > > + if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) > + return qcom_ice_evict_key(msm_host->ice, slot); > + > /* Only AES-256-XTS has been tested so far. */ > cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; > if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS || > cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) > return -EINVAL; > > - if (cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE) > - return qcom_ice_program_key(msm_host->ice, > - QCOM_ICE_CRYPTO_ALG_AES_XTS, > - QCOM_ICE_CRYPTO_KEY_SIZE_256, > - cfg->crypto_key, > - cfg->data_unit_size, slot); > - else > - return qcom_ice_evict_key(msm_host->ice, slot); > + return qcom_ice_program_key(msm_host->ice, > + QCOM_ICE_CRYPTO_ALG_AES_XTS, > + QCOM_ICE_CRYPTO_KEY_SIZE_256, > + cfg->crypto_key, > + cfg->data_unit_size, slot); > } > > #else /* CONFIG_MMC_CRYPTO */ > > static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > -- > 2.47.1 >
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e00208535bd1..319f0ebbe652 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1865,24 +1865,24 @@ static int sdhci_msm_program_key(struct cqhci_host *cq_host, struct sdhci_host *host = mmc_priv(cq_host->mmc); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); union cqhci_crypto_cap_entry cap; + if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) + return qcom_ice_evict_key(msm_host->ice, slot); + /* Only AES-256-XTS has been tested so far. */ cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS || cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) return -EINVAL; - if (cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE) - return qcom_ice_program_key(msm_host->ice, - QCOM_ICE_CRYPTO_ALG_AES_XTS, - QCOM_ICE_CRYPTO_KEY_SIZE_256, - cfg->crypto_key, - cfg->data_unit_size, slot); - else - return qcom_ice_evict_key(msm_host->ice, slot); + return qcom_ice_program_key(msm_host->ice, + QCOM_ICE_CRYPTO_ALG_AES_XTS, + QCOM_ICE_CRYPTO_KEY_SIZE_256, + cfg->crypto_key, + cfg->data_unit_size, slot); } #else /* CONFIG_MMC_CRYPTO */ static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,