From patchwork Mon Jul 24 12:45:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13324601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FACAC0015E for ; Mon, 24 Jul 2023 12:47:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbjGXMrg (ORCPT ); Mon, 24 Jul 2023 08:47:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230213AbjGXMrU (ORCPT ); Mon, 24 Jul 2023 08:47:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9473719A0; Mon, 24 Jul 2023 05:47:13 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BA96261152; Mon, 24 Jul 2023 12:47:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50B3DC433CA; Mon, 24 Jul 2023 12:47:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690202832; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UsZgLm8NdUWGW1yuLTFg4d2z0IF24qUF4q1+KeNH02fBNnDtrN6rxOAe1J7HKvOMx iaFZjxP6jjbIPBksQBtSoJBkVELmsVOvEWNdEeByu0VB0I60fPObqLdoQXfcknpmQp KEC3h6GMHO4lbhGK0ScVnYFqw6GE0pEFaPmGLc97TIuxMsdDobHd/rYKuupmCh37LR TNhKysMlR1lwhEaLyd0R4HO5U99zEJc+WYNUN0lUe5Tb247LeQrnv5r9f3xFP/C5oP XUqrmGMKGItUTjbq0a+QoBWX2CN+oNFT/RozpP9zaHIIBbGUeHxLAOcYDYr4BdllDi VO3XQWlkbyqGg== From: Mark Brown Date: Mon, 24 Jul 2023 13:45:49 +0100 Subject: [PATCH v2 02/35] arm64: Document boot requirements for Guarded Control Stacks MIME-Version: 1.0 Message-Id: <20230724-arm64-gcs-v2-2-dc2c1d44c2eb@kernel.org> References: <20230724-arm64-gcs-v2-0-dc2c1d44c2eb@kernel.org> In-Reply-To: <20230724-arm64-gcs-v2-0-dc2c1d44c2eb@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-099c9 X-Developer-Signature: v=1; a=openpgp-sha256; l=1640; i=broonie@kernel.org; h=from:subject:message-id; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; b=owGbwMvMwMWocq27KDak/QLjabUkhpR9Re1H+AzvfFlc8aNW9m2KzIIncfmbO1Pmhk29GNDSN2WT iPjyTkZjFgZGLgZZMUWWtc8yVqWHS2yd/2j+K5hBrEwgUxi4OAXgImfY/xe7SUWdCuAuK+x0eVtQKM AmNDf336lTl9WnH6nIncoUvvhUxc1JNjFT3WZUtJ7xlnu3bMe/gDfy3/K1A6Y3XRZ5blgzcbbmQ1aJ Jz6OX5JnRa9qmfi2rvjN+ZarKgq7kyP6K1O+rNii+qRck006zUilM4/9mUR6neiszd/ibpwr0NSvWm WQxXZUU/LnjK63jruYQ1/xXpPmf+SZl//de8V36bQ3XVV7J5S+4A0NmrvmNWeYolC5lVC7eTSPReaE PdOs73g2W60WdjA8+1U3rXnljWXSmx0f7Nvx5ZaxhOOUC6v6lBeGpxRJnzMG+nIB9xfP9Zl3Nv1zOO 7m9OuLjdxmL7s7mhteXl5Vq7kZAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org FEAT_GCS introduces a number of new system registers, we require that access to these registers is not trapped when we identify that the feature is detected. Signed-off-by: Mark Brown --- Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..de3679770c64 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -411,6 +411,28 @@ Before jumping into the kernel, the following conditions must be met: - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. + - For features with Guarded Control Stacks (FEAT_GCS): + + - If EL3 is present: + + - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1. + + - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1. + + - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented