From patchwork Mon Aug 7 22:00:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13345100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8972CC04FDF for ; Mon, 7 Aug 2023 22:01:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230440AbjHGWBz (ORCPT ); Mon, 7 Aug 2023 18:01:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230325AbjHGWBv (ORCPT ); Mon, 7 Aug 2023 18:01:51 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 779F6DE; Mon, 7 Aug 2023 15:01:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 740B06223A; Mon, 7 Aug 2023 22:01:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F0BDC433B6; Mon, 7 Aug 2023 22:01:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691445703; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Th1Z9bVZmowOrXA//qqPzkg9/0FflEIxNHKJhCLc/z2CQKnCJG5DosJLmUmw+onOh 5wLMapny4nRmClsBtHWzRgWcJXonhkPSO7plqiyOioxX6Qcp0BvT/AF0SHf2sM/IMp EEY26EU0UBmOKFPHBAMR0lQykh44yiIDEHVxSv1jZVICoDECbdj7TX7aIaUxhuvfFK XyKCA0rMYu2wlIE8YWhBZ/zI0MdfI3gG4epqjukMR7Eiu/3uSA0dUimExMOs3+1h2n LEmAFbygEjYI8+6wW4f6U2Zu0TZdKx7s7Ayq57giRcnMlN//heaQNKqA+mNvFJoD0r Qn+uRSkkrlJsQ== From: Mark Brown Date: Mon, 07 Aug 2023 23:00:07 +0100 Subject: [PATCH v4 02/36] arm64: Document boot requirements for Guarded Control Stacks MIME-Version: 1.0 Message-Id: <20230807-arm64-gcs-v4-2-68cfa37f9069@kernel.org> References: <20230807-arm64-gcs-v4-0-68cfa37f9069@kernel.org> In-Reply-To: <20230807-arm64-gcs-v4-0-68cfa37f9069@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1640; i=broonie@kernel.org; h=from:subject:message-id; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBk0WmZbLyQWkqJ2tbfJHVr9HGRMWp3m8IuCBxbUpN3 n4AEtaqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZNFpmQAKCRAk1otyXVSH0EVvB/ 448mJqyXS/1bkj4UVvUEvHo+tLm9pbwH9qPL7ePhWt9agCi1fJ3JvunySZvTrX8Zho9v8xFt8Blvpo IGLmxat/yF6dJKfZitd8oFiPY3cyXLYyUTsiqAvGSn3eQhE7PBKDKLeZEFQ/5EtfUk8L16dNMWjEav qqN1kvOxX6qp9+KPrN8lcFPHRYvjeM3psViv9GfuFs6B2bA4FLjdvNgrH9yOW8o+pVsaZNxPwZmpdL 5bPOa43T95OYMnLHGAXje8MqHz0FGi+O9tUVO2NMSmMmjMnhFXzdMJtHkAcRqhw6yUcGkSykzK2sSI gI0CAqT/hhBf+DnJw394T4Q2tN4/vs X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org FEAT_GCS introduces a number of new system registers, we require that access to these registers is not trapped when we identify that the feature is detected. Signed-off-by: Mark Brown --- Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..de3679770c64 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -411,6 +411,28 @@ Before jumping into the kernel, the following conditions must be met: - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. + - For features with Guarded Control Stacks (FEAT_GCS): + + - If EL3 is present: + + - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1. + + - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1. + + - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented