From patchwork Tue Aug 22 13:56:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13360826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3BC2EE49A4 for ; Tue, 22 Aug 2023 14:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236287AbjHVODc (ORCPT ); Tue, 22 Aug 2023 10:03:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236265AbjHVODa (ORCPT ); Tue, 22 Aug 2023 10:03:30 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF5DDCF8; Tue, 22 Aug 2023 07:03:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 458546576F; Tue, 22 Aug 2023 14:03:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE1C6C433BF; Tue, 22 Aug 2023 14:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692713001; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eHReH606MpLs9WboH5th6rKpbf9I9vL5tswCQ5jkPZnrlZ7AfdBkZEkS27jO3R7bx 5ZhSqlGdPSJC1AnUBS7MXVB902vrcrbLcJb8Zs00juzWs8U2B9uroKHIOE2XLazJDB 9ztduMXB5WfJbuLkda4t+vqiMs7BW+1AzIAJmtbbCEjhJ0TTXVgUnX82gXhvfugmLm YI9QkNM8qRtoaHYJqpkc7ABdPfR/gXMZbXBjqgEQIIX2LUdiXLiA8unGNzfoXHuHgi JH9+It5iDHuis7w58rDW2X1NLSxdWaeHDoEPPNhW6w1o7G0KyABEoe6bevzgq1yKgc 4gymJqKuXWHFQ== From: Mark Brown Date: Tue, 22 Aug 2023 14:56:36 +0100 Subject: [PATCH v5 03/37] arm64: Document boot requirements for Guarded Control Stacks MIME-Version: 1.0 Message-Id: <20230822-arm64-gcs-v5-3-9ef181dd6324@kernel.org> References: <20230822-arm64-gcs-v5-0-9ef181dd6324@kernel.org> In-Reply-To: <20230822-arm64-gcs-v5-0-9ef181dd6324@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1640; i=broonie@kernel.org; h=from:subject:message-id; bh=Z3injfV8td0LqFLeGew+/6AX1Y4kpAJIpTs5MPlZTRs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBk5L/y2wEbbpTgwviy3ePcPDlfAKr3otxFttaAJqc3 Tzt7CWaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZOS/8gAKCRAk1otyXVSH0B2qB/ 4qKUbrZgSkHAikeSJ1Q2Qe1JgckUv+ylVkQAlJsM1vP5WJ/a19okUM0dEMBFMGSGk3GgdMvYp0/VLz TCQvGYwMn/AVD/JLwjPUxPaqP9vTmCgGF11MYh/GcBQEQmxOws0ARr0ENRppRs5aWzbv6t4VnX9Ua/ 8Qdd6hJmWNLCq5c/j3w2ac+x5kgbxD/Nfi3tQZDxYWNSI9wl/EizR/OsLEl+/3QHhujqe5uICYT7Do bbkKtzB5gZ799TXD+6mIE+hNkWybR2WWc60wzSw29JJNl/QY7MjwD8MYb6RTZj8PlOmK/HL1dngSgU GWNFr6ziyz/26uENbCyBe8KQYcV+BV X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org FEAT_GCS introduces a number of new system registers, we require that access to these registers is not trapped when we identify that the feature is detected. Signed-off-by: Mark Brown --- Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..de3679770c64 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -411,6 +411,28 @@ Before jumping into the kernel, the following conditions must be met: - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. + - For features with Guarded Control Stacks (FEAT_GCS): + + - If EL3 is present: + + - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1. + + - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1. + + - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1. + + - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented