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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF0000000E.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 05:59:36 +0000 Received: from shatadru.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Jun 2024 00:59:29 -0500 From: Dhananjay Ugwekar To: , , , , , , , , , , , , , , , , , CC: , , , , , , , , , Dhananjay Ugwekar Subject: [PATCH v3 00/10] Add per-core RAPL energy counter support for AMD CPUs Date: Mon, 24 Jun 2024 05:58:57 +0000 Message-ID: <20240624055907.7720-1-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000E:EE_|LV3PR12MB9215:EE_ X-MS-Office365-Filtering-Correlation-Id: cdfdd9a2-690a-46c8-2b8f-08dc9412d40a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|7416011|82310400023|1800799021|921017; X-Microsoft-Antispam-Message-Info: TRHLlFMs65xjoZ1Uw9Jqcq6SEO4US4TtokyLWXUPwXrhd6Op5bfWr1XkUhrHjB38C2AS9Vj39Pxt2iecT4dHkw68bPwfvYO2liKn+Jz+G0CdgECNn9ifvv2b8aPdXCVGMEbO1J95KJFQDS46p0zn7KVdD0o2KGdXtHuGnAo4BQBjPe6UC28UNhh9pgo8CEablBW6KtMX+DX0uFp1sgO5oS8eEceve9Bd1OMnuBpj3rG83NTu7rVr1FsXBW28ZM+E6t6xpx/q19/9QnIubg+VgMArdvLPLbRwDs6LsRFSKkPVm6mD6XD+XbcoNh/yLY99NGizWUWVZAr97vZw915JAweLv6umQlxzlRFUa64gkutQENIQA5Y/DmDD3QwEmM41la7GSR4cNfFTHI3nygYfGMi3+GncOFcBLnGGHGzEPtj2nuisYFr9cTpK4QgePjASn13OUoajBM8+nzUFvkGNnmOMmYpg8Qm5WuxZBbItOGAebAlC4zWFAHGpfAdIXbdCabKeRW0MXSCTv3Ae9DdRH2h1QoavHs1iGG6XHm3FIYwUFCONkgEGU/d8TeBMF89ypVFKDpbFNPGI0KJ3dfuecetW7PuotKPzAV+IOly03UU1li4HWxI881K+ClLpK4yVgtt/7uGh2NykgUxctLSvMGq+pUpHsgLFaC2h1K5VN+mZEoYGkex99YFRdugNfP7YSDAWxUlBPm5HCuoP+aNqNNX+Zls3pGiv5afb2bKY6jte2Fgpr42Csq8FRUciH90WxT/m8J+LqBz20AprnE0CZsziq805npcl45VWqRRNKYlBsW5HfXuJ6oW1LS0t0ccnjdyjJw9rHcfkKsARfgUuDudcS5rBaZw3bz0AF51HULpSOZx/JfJELiaKvBgB2YgS3K9V87yklZc0JngHc7IEFBzzNdoiB+iMHVh/CslDKdmq9fVl64zwzKfKsw/wvFUA6kS5lglra4Ydzt+G4vu3KtH5/68b0EvN1YZa/hTD6Srs4MMwA9DMIRVL7sRGiZNSEBF8O8cRKdtFsLJyrkcd8xEmzUW7Wgw8iN03iFnquglTDDjGbmWvi2Bl2DfT1PlcN/aMthOuS/ZTWBe7eB14JPFfzzJaCsEBpHC9C/iXE6ACfKvSELwwlu1RmbWcNsQLJV+us8YdxTKsqtK++EesBTQ8LR1WXIs26MEZDOrfHauQGz/gwCDeYrAngcmGYZCVEXpUn8dzaVxntAjASNlNuPyD8nd0WnOfjgenEpRXrJ6zKnEc9a343AAMASTwvPBIxw5aUGTzO1umXApofX5IvDgiKmUrdcypFF79YK5W/z+CvmDPMNDbrgazIF9DVEneGBQ1BlPTrja6BEBXUGJImp0xYxUmoAWC9HNSuewcrtE83cum1WJw6PU9mZbjTU/2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(376011)(7416011)(82310400023)(1800799021)(921017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 05:59:36.6588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdfdd9a2-690a-46c8-2b8f-08dc9412d40a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9215 Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed [1], due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU. This patchset adds a new "power_per_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-per-core" event. Tested the package level and core level PMU counters with workloads pinned to different CPUs. Results with workload pinned to CPU 1 in Core 1 on an AMD Zen4 Genoa machine: $ perf stat -a --per-core -e power_per_core/energy-per-core/ -- sleep 1 Performance counter stats for 'system wide': S0-D0-C0 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C1 1 5.72 Joules power_per_core/energy-per-core/ S0-D0-C2 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C3 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C4 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C5 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C6 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C7 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C8 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C9 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C10 1 0.02 Joules power_per_core/energy-per-core/ [1]: https://lore.kernel.org/lkml/3e766f0e-37d4-0f82-3868-31b14228868d@linux.intel.com/ This patchset applies cleanly on top of v6.10-rc4 as well as latest tip/master. v3 changes: * Patch 1 added to introduce the logical_core_id which is unique across the system (Prateek) * Use the unique topology_logical_core_id() instead of topology_core_id() (which is only unique within a package on tested AMD and Intel systems) in Patch 10 v2 changes: * Patches 6,7,8 added to split some changes out of the last patch * Use container_of to get the rapl_pmus from event variable (Rui) * Set PERF_EV_CAP_READ_ACTIVE_PKG flag only for pkg scope PMU (Rui) * Use event id 0x1 for energy-per-core event (Rui) * Use PERF_RAPL_PER_CORE bit instead of adding a new flag to check for per-core counter hw support (Rui) Dhananjay Ugwekar (9): perf/x86/rapl: Fix the energy-pkg event for AMD CPUs perf/x86/rapl: Rename rapl_pmu variables perf/x86/rapl: Make rapl_model struct global perf/x86/rapl: Move cpumask variable to rapl_pmus struct perf/x86/rapl: Add wrapper for online/offline functions perf/x86/rapl: Add an argument to the cleanup and init functions perf/x86/rapl: Modify the generic variable names to *_pkg* perf/x86/rapl: Remove the global variable rapl_msrs perf/x86/rapl: Add per-core energy counter support for AMD CPUs K Prateek Nayak (1): x86/topology: Introduce topology_logical_core_id() Documentation/arch/x86/topology.rst | 4 + arch/x86/events/rapl.c | 418 ++++++++++++++++++-------- arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + 6 files changed, 305 insertions(+), 121 deletions(-) Tested-by: K Prateek Nayak