From patchwork Tue May 9 19:01:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kees Cook X-Patchwork-Id: 9718859 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8D5DE60236 for ; Tue, 9 May 2017 19:01:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81FD028450 for ; Tue, 9 May 2017 19:01:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 768332845C; Tue, 9 May 2017 19:01:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id A1A6A28450 for ; Tue, 9 May 2017 19:01:43 +0000 (UTC) Received: (qmail 5131 invoked by uid 550); 9 May 2017 19:01:40 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 4083 invoked from network); 9 May 2017 19:01:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ql/5XkDNPwIhTxtQErexdK5RA15BuSqZBzY2hMN7Wcs=; b=WvFCqpw8C6uLC+52lVzQHITz8e9cG+56h6uAW+iNsF9VtM79Lyk3IefdQQPVQlkb5Z 692Bm0g31d/pNiz2N1jdCYzYJDWE3y0wVIh0DzRSI48S9Wbl0tg3ZSQqHK6sjiD9lhWp 9I3T+LPd4kLTEeGdQJFUB4zFASeCJcisNFhCA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ql/5XkDNPwIhTxtQErexdK5RA15BuSqZBzY2hMN7Wcs=; b=g8MCu8cUzeSs2G8DV90OZz+wgd04sSDUk4z77PRevVt0pdQc6K9tACuJfxVEwB+I08 rPeqrD2A+OxbBipmqC0u98AiNhnMF9B5v61SlKWSxcjHgYigvwd8Fk4vVQ8zgd7qwOfe izb58EIIUXzlNqZhxNeH1C3E0rAsJOaWGgVV43GH9IVL79oHW0wWWTth5aJra85cP5dT FcNQPxfSAK2xK56qZR89VACSiqhZPy04RIycSQ1mYLUdHaMbseJrA4NGR7fEkOHYP6bv sAqPiIUZ5DkYNwrRDYNONmbXzzSrL/4qUYAM5GO5KUlSKa+XeqmvjaGQX7hOUftPOvcz h9oA== X-Gm-Message-State: AODbwcDQGFwwLUwcn9JCgvIcxtA6Z4GIS8t/47JLCuA17nR1XEyHAhbL 3drqxsfR2xjtEUEH X-Received: by 10.98.218.89 with SMTP id w25mr1548889pfl.133.1494356487328; Tue, 09 May 2017 12:01:27 -0700 (PDT) From: Kees Cook To: linux-kernel@vger.kernel.org Cc: Kees Cook , Peter Zijlstra , Josh Poimboeuf , PaX Team , Jann Horn , Eric Biggers , Christoph Hellwig , "axboe@kernel.dk" , James Bottomley , Elena Reshetova , Hans Liljestrand , David Windsor , "x86@kernel.org" , Ingo Molnar , Arnd Bergmann , Greg Kroah-Hartman , "David S. Miller" , Rik van Riel , linux-arch , kernel-hardening@lists.openwall.com Date: Tue, 9 May 2017 12:01:22 -0700 Message-Id: <1494356483-81678-2-git-send-email-keescook@chromium.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494356483-81678-1-git-send-email-keescook@chromium.org> References: <1494356483-81678-1-git-send-email-keescook@chromium.org> Subject: [kernel-hardening] [PATCH v4 1/2] x86/asm: Add suffix macro for GEN_*_RMWcc() X-Virus-Scanned: ClamAV using ClamSMTP The coming x86 refcount protection needs to be able to add trailing instructions to the GEN_*_RMWcc() operations. This extracts the difference between the goto/non-goto cases so the helper macros can be defined outside the #ifdef cases. Additionally adds argument naming to the resulting asm for referencing from suffixed instructions. Signed-off-by: Kees Cook --- arch/x86/include/asm/rmwcc.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/rmwcc.h b/arch/x86/include/asm/rmwcc.h index 661dd305694a..3e96f9a56b6d 100644 --- a/arch/x86/include/asm/rmwcc.h +++ b/arch/x86/include/asm/rmwcc.h @@ -8,18 +8,15 @@ #define __GEN_RMWcc(fullop, var, cc, ...) \ do { \ asm_volatile_goto (fullop "; j" #cc " %l[cc_label]" \ - : : "m" (var), ## __VA_ARGS__ \ + : : [counter] "m" (var), ## __VA_ARGS__ \ : "memory" : cc_label); \ return 0; \ cc_label: \ return 1; \ } while (0) -#define GEN_UNARY_RMWcc(op, var, arg0, cc) \ - __GEN_RMWcc(op " " arg0, var, cc) +#define __BINARY_RMWcc_ARG " %1, " -#define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \ - __GEN_RMWcc(op " %1, " arg0, var, cc, vcon (val)) #else /* defined(__GCC_ASM_FLAG_OUTPUTS__) || !defined(CC_HAVE_ASM_GOTO) */ @@ -29,17 +26,26 @@ cc_label: \ do { \ bool c; \ asm volatile (fullop ";" CC_SET(cc) \ - : "+m" (var), CC_OUT(cc) (c) \ + : [counter] "+m" (var), CC_OUT(cc) (c) \ : __VA_ARGS__ : "memory"); \ return c; \ } while (0) +#define __BINARY_RMWcc_ARG " %2, " + +#endif /* defined(__GCC_ASM_FLAG_OUTPUTS__) || !defined(CC_HAVE_ASM_GOTO) */ + #define GEN_UNARY_RMWcc(op, var, arg0, cc) \ __GEN_RMWcc(op " " arg0, var, cc) +#define GEN_UNARY_SUFFIXED_RMWcc(op, suffix, var, arg0, cc) \ + __GEN_RMWcc(op " " arg0 "\n\t" suffix, var, cc) + #define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \ - __GEN_RMWcc(op " %2, " arg0, var, cc, vcon (val)) + __GEN_RMWcc(op __BINARY_RMWcc_ARG arg0, var, cc, vcon (val)) -#endif /* defined(__GCC_ASM_FLAG_OUTPUTS__) || !defined(CC_HAVE_ASM_GOTO) */ +#define GEN_BINARY_SUFFIXED_RMWcc(op, suffix, var, vcon, val, arg0, cc) \ + __GEN_RMWcc(op __BINARY_RMWcc_ARG arg0 "\n\t" suffix, var, cc, \ + vcon (val)) #endif /* _ASM_X86_RMWcc */