@@ -24,6 +24,10 @@
#define wmb() asm volatile("sfence" ::: "memory")
#endif
+/* prevent speculative execution past this barrier */
+#define ifence() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
+ "lfence", X86_FEATURE_LFENCE_RDTSC)
+
#ifdef CONFIG_X86_PPRO_FENCE
#define dma_rmb() rmb()
#else
@@ -214,8 +214,7 @@ static __always_inline unsigned long long rdtsc_ordered(void)
* that some other imaginary CPU is updating continuously with a
* time stamp.
*/
- alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
- "lfence", X86_FEATURE_LFENCE_RDTSC);
+ ifence();
return rdtsc();
}
The new barrier, 'ifence', ensures that speculative execution never crosses the fence. Previously the kernel only needed this fence in 'rdtsc_ordered', but now it is also proposed as a mitigation against Spectre variant1 attacks. When used it needs to be placed in the success path after a bounds check i.e.: if (x < max) { ifence(); val = array[x]; } else return -EINVAL; With this change the cpu will never issue speculative reads of 'array + x' with values of x >= max. 'ifence', via 'ifence_array_ptr', is an opt-in fallback to the default mitigation provided by '__array_ptr'. It is also proposed for blocking speculation in the 'get_user' path to bypass 'access_ok' checks. For now, just provide the common definition for later patches to build upon. Suggested-by: Peter Zijlstra <peterz@infradead.org> Suggested-by: Alan Cox <alan.cox@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Signed-off-by: Elena Reshetova <elena.reshetova@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- arch/x86/include/asm/barrier.h | 4 ++++ arch/x86/include/asm/msr.h | 3 +-- 2 files changed, 5 insertions(+), 2 deletions(-)