From patchwork Tue Mar 13 19:51:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salvatore Mesoraca X-Patchwork-Id: 10280653 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ADD9C602C2 for ; Tue, 13 Mar 2018 19:52:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A406283ED for ; Tue, 13 Mar 2018 19:52:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 982B528418; Tue, 13 Mar 2018 19:52:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id AEC0128438 for ; Tue, 13 Mar 2018 19:51:54 +0000 (UTC) Received: (qmail 13873 invoked by uid 550); 13 Mar 2018 19:51:52 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 13833 invoked from network); 13 Mar 2018 19:51:51 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=QUuliaqvvd9yYQ8CUodAdPCoYwxKNVGuRakunjvw/uU=; b=uksPBk40kAMEhdhBSjQS9Dg9EvA0Arx4hCR7CqdwuqSO7MPIDjlcqrqTKhwvTv26uw jgJVJW8WdVOUFB8C88yzfOqi/bZ83z/13w7zzZ125ONPehbgDjW6XNU3B4bR/QNECd/v Gi5s/hTr6ISr4O5+lDFLRDeHQRBDyWEQSpqgjdN61xptv5Vzh4RamMlADPAAWRL0Yawk 0ON/uloXw2WlVPpbu+SbyYbYZBvQtWtdMp/aVtSx3rf5137ofJP4a6qGk1v/3EG4WQyK pNHHrFEtKcdTvbJwRt19tvturXwS2xztrVBOos9EXOzaW431tfe2Fv26/rZ+Hn0emVP+ /sUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=QUuliaqvvd9yYQ8CUodAdPCoYwxKNVGuRakunjvw/uU=; b=cJpQiVyX+IVdeBBEI6By0Zuj/yoSzDzNYoK5287ELt+ruCjKTsT1UZoZ3KmMcZByrY GWdyONWzOp2JzDrDql/1kdXbBNqmHllNPmy0i9aVH512E0dQrr5JxHn4zffm3uR1Jn7a wlB0MDjzvw7n42qGXULMLaUHzeNalxiHraDDbmBLO19Tq8OqeWqM84RAQRwbwJN9m9Xm 9A+Mbx0CsYks+st/dOrjpTyxMIGOdd2nR2DUC73zaRABQ/ZQQA7J54z3NFIXoz3SONEV JmxOE9ile5T5qoZNaShyGuRYJ1+qMf1b1EKOJNH/5cfx7csGRrEm4i7BrDdvNhY/btMw gE2A== X-Gm-Message-State: AElRT7ErSRS2unujAEwkz2AkvQyrmVtVJLAngMF2YJzFUlAjJ1s06BHT sOzDO9pkQdW5wLyfak6x1nU= X-Google-Smtp-Source: AG47ELv24KbKryLce9k0Z/11EdFzTbNcmkdlV8rg+jGwcBjC+SlO+ttG0loOc3ee9RYr2sOCt/tNmw== X-Received: by 10.223.186.140 with SMTP id p12mr1681196wrg.162.1520970700640; Tue, 13 Mar 2018 12:51:40 -0700 (PDT) From: Salvatore Mesoraca To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, kernel-hardening@lists.openwall.com, David Airlie , Jani Nikula , Joonas Lahtinen , Kees Cook , Rodrigo Vivi , Salvatore Mesoraca Subject: [PATCH] drm/i915: drop various VLAs in i915_debugfs.c Date: Tue, 13 Mar 2018 20:51:28 +0100 Message-Id: <1520970688-19683-1-git-send-email-s.mesoraca16@gmail.com> X-Mailer: git-send-email 1.9.1 X-Virus-Scanned: ClamAV using ClamSMTP Avoid 3 VLAs[1] by using real constant expressions instead of variables. The compiler should be able to optimize the original code and avoid using any actual VLAs. Anyway this change is useful because it will avoid a false positives with -Wvla, it might also help the compiler generating better code. [1] https://lkml.org/lkml/2018/3/7/621 Signed-off-by: Salvatore Mesoraca --- drivers/gpu/drm/i915/i915_debugfs.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e968aea..bf0a8e3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4259,19 +4259,20 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, i915_cache_sharing_get, i915_cache_sharing_set, "%llu\n"); +#define CHERRYVIEW_SS_MAX 2 + static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { - int ss_max = 2; int ss; - u32 sig1[ss_max], sig2[ss_max]; + u32 sig1[CHERRYVIEW_SS_MAX], sig2[CHERRYVIEW_SS_MAX]; sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); - for (ss = 0; ss < ss_max; ss++) { + for (ss = 0; ss < CHERRYVIEW_SS_MAX; ss++) { unsigned int eu_cnt; if (sig1[ss] & CHV_SS_PG_ENABLE) @@ -4290,15 +4291,17 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, } } +#define GEN10_S_MAX 6 +#define GEN10_SS_MAX 4 + static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { const struct intel_device_info *info = INTEL_INFO(dev_priv); - int s_max = 6, ss_max = 4; int s, ss; - u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2]; + u32 s_reg[GEN10_S_MAX], eu_reg[2 * GEN10_S_MAX], eu_mask[2]; - for (s = 0; s < s_max; s++) { + for (s = 0; s < GEN10_S_MAX; s++) { /* * FIXME: Valid SS Mask respects the spec and read * only valid bits for those registers, excluding reserverd @@ -4320,7 +4323,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, GEN9_PGCTL_SSB_EU210_ACK | GEN9_PGCTL_SSB_EU311_ACK; - for (s = 0; s < s_max; s++) { + for (s = 0; s < GEN10_S_MAX; s++) { if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) /* skip disabled slice */ continue; @@ -4328,7 +4331,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); sseu->subslice_mask = info->sseu.subslice_mask; - for (ss = 0; ss < ss_max; ss++) { + for (ss = 0; ss < GEN10_SS_MAX; ss++) { unsigned int eu_cnt; if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) @@ -4345,12 +4348,15 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, } } +#define GEN9_S_MAX 3 +#define GEN9_SS_MAX 4 + static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { - int s_max = 3, ss_max = 4; + int s_max = GEN9_S_MAX, ss_max = GEN9_SS_MAX; int s, ss; - u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; + u32 s_reg[GEN9_S_MAX], eu_reg[2*GEN9_S_MAX], eu_mask[2]; /* BXT has a single slice and at most 3 subslices. */ if (IS_GEN9_LP(dev_priv)) {