From patchwork Mon Aug 14 12:53:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9898825 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DE4FF602BA for ; Mon, 14 Aug 2017 12:57:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D3241285E3 for ; Mon, 14 Aug 2017 12:57:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C7835285F2; Mon, 14 Aug 2017 12:57:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 479AD28618 for ; Mon, 14 Aug 2017 12:57:17 +0000 (UTC) Received: (qmail 26158 invoked by uid 550); 14 Aug 2017 12:55:39 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 23739 invoked from network); 14 Aug 2017 12:55:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nyw6d4f5dcGfTYsO8KTu3IIZ4cl45ODolMMmmSoyNiU=; b=WmI0yfdPgU5Y6Tjc+fyb20UKoB64nZ5z30u8WTYcb6j7UA/e8QMvY8EZQyN/U6cYsj UeGUxDolqvm+1wbSdn+Uay6v9mu6Z36qPdAGzVwkrn34bANHVvRhN21BSjnee3csf7yP y8IFW5bIbWX7mWSB4ffHMEfj6mhERC8Alvx4M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nyw6d4f5dcGfTYsO8KTu3IIZ4cl45ODolMMmmSoyNiU=; b=fsEj6PBhaLC10vuqbt5syTe4SHhu00S26b3eLrPTvZx4PY+FEqaoRUvahhSsJdxxCS Q7HetuxiyjJqZk2BmbWonIjGdrAWN7xSwRvuiRyVF8kWuNd9J7V2/HcKBowZ2+aTr4Vw MPZ4LZgRSFtA8Q5iJpEZd4yRju7cLfhTOq0Y0MZ9WBqzWRR5yWPwNVJhGsbHqmfNSJ6V rAbwJtjlqwrSUdRWfYwfW8BhF9/X+l9Qb8LrVZyta3OC//RWvnKlybpyVqB271OBo8ld wfgeujaHczEgkzQBThi91Gu1RzqwCQ+bxjfMPTJtTWEGJW0T3DDWAzyyAosAhw4M/hjt PzKw== X-Gm-Message-State: AHYfb5jEzOhnbE05Zmw1USIEg0mVZlNJy6MoJ52QUX4+3CYsZwAAWtqa 8YvI9h1WlmYeSkfTnSjRAQ== X-Received: by 10.223.164.208 with SMTP id h16mr18266723wrb.100.1502715311999; Mon, 14 Aug 2017 05:55:11 -0700 (PDT) From: Ard Biesheuvel To: kernel-hardening@lists.openwall.com Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Arnd Bergmann , Nicolas Pitre , Russell King , Kees Cook , Thomas Garnier , Marc Zyngier , Mark Rutland , Tony Lindgren , Matt Fleming , Dave Martin Date: Mon, 14 Aug 2017 13:53:55 +0100 Message-Id: <20170814125411.22604-15-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170814125411.22604-1-ard.biesheuvel@linaro.org> References: <20170814125411.22604-1-ard.biesheuvel@linaro.org> Subject: [kernel-hardening] [PATCH 14/30] arm-soc: various: replace open coded VA->PA calculation of pen_release X-Virus-Scanned: ClamAV using ClamSMTP This replaces a few copies of the open coded calculations of the physical address of 'pen_release' in the secondary startup code of a couple of platforms. This ensures these quantities are invariant under runtime relocation. Cc: Russell King Signed-off-by: Ard Biesheuvel --- arch/arm/mach-prima2/headsmp.S | 11 +++-------- arch/arm/mach-spear/headsmp.S | 11 +++-------- arch/arm/mach-sti/headsmp.S | 10 +++------- arch/arm/plat-versatile/headsmp.S | 9 +-------- 4 files changed, 10 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S index 209d9fc5c16c..070df700bb38 100644 --- a/arch/arm/mach-prima2/headsmp.S +++ b/arch/arm/mach-prima2/headsmp.S @@ -9,6 +9,8 @@ #include #include +#include + /* * SIRFSOC specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're @@ -17,10 +19,7 @@ ENTRY(sirfsoc_secondary_startup) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -31,7 +30,3 @@ pen: ldr r7, [r6] */ b secondary_startup ENDPROC(sirfsoc_secondary_startup) - - .align -1: .long . - .long pen_release diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S index c52192dc3d9f..4da01b103f33 100644 --- a/arch/arm/mach-spear/headsmp.S +++ b/arch/arm/mach-spear/headsmp.S @@ -13,6 +13,8 @@ #include #include +#include + __INIT /* @@ -23,10 +25,7 @@ ENTRY(spear13xx_secondary_startup) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -40,8 +39,4 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup - - .align -1: .long . - .long pen_release ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S index e0ad451700d5..cdf3442f397b 100644 --- a/arch/arm/mach-sti/headsmp.S +++ b/arch/arm/mach-sti/headsmp.S @@ -16,6 +16,8 @@ #include #include +#include + /* * ST specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're @@ -24,10 +26,7 @@ ENTRY(sti_secondary_startup) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -38,6 +37,3 @@ pen: ldr r7, [r6] */ b secondary_startup ENDPROC(sti_secondary_startup) - -1: .long . - .long pen_release diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index 40f27e52de75..0f2a5eddac5a 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -21,10 +21,7 @@ ENTRY(versatile_secondary_startup) ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 bic r0, #0xff000000 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -34,8 +31,4 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup - - .align -1: .long . - .long pen_release ENDPROC(versatile_secondary_startup)