From patchwork Sun Sep 3 12:07:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9936151 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EF1A16037D for ; Sun, 3 Sep 2017 12:11:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0E06286A9 for ; Sun, 3 Sep 2017 12:11:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D599C286B3; Sun, 3 Sep 2017 12:11:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id AF18A286A9 for ; Sun, 3 Sep 2017 12:11:51 +0000 (UTC) Received: (qmail 16166 invoked by uid 550); 3 Sep 2017 12:09:28 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 16043 invoked from network); 3 Sep 2017 12:09:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uVywaPQS5LTACUk8Qqqc9rpOI/jN/LtItDJIs1KfvSQ=; b=UpJOGI35r9shwDLHd1s6hFwACOCDkav/rzNmYO34lX0RhmiSV1i+iNumzI+8YRbSMb CclCqa9qBPrFbbcs+Tkq0GPofctCIHS+K7I0tzt/x9heT/yp4AA9TO+edsmIMV3wB4ju 7illWbiajzEJSFMddrQl52+LINKPLGAFpT8h0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uVywaPQS5LTACUk8Qqqc9rpOI/jN/LtItDJIs1KfvSQ=; b=N1gCLwhK8xNltgRLUmKr90n3DH4U85Zcg9/NHv45JnIM5RA0579UbRkxJ1QNYE2aKI XNiOrkyf/rESTEwIQMLmZQUAeyTDYG4yfJ1V/lA1iDDHrJWORRsDKI3ZPPzX8Di1SVlJ 7FE5M8sucq0lDAbt4bJPM9gf3R4L0EYi0B3w8xdBJXxSdQNT0ptdK94NP1pwcI5ROErC UxdKFeToYtrhg+/yxptN0X3FXzAvwINFiaCJpMhv8cmseCYVWWcU86BwRWLoZPgTSUKN +TRz5Rsz47EaSKSVM6BpVmr8DoBFGOqF41RvZuGZO0Ms3S2Nea9eTEfF1roQSNodpg7+ 0u3w== X-Gm-Message-State: AHPjjUgRMxFxNk0/5bgEwGDy+QIzIzCTrvEPBW/bqClbFL2DRiN9NN7g 1HD0e1gE7dK5IAeU X-Google-Smtp-Source: ADKCNb7AmZk8Ezzk/hPcEmNEJplJbmGdYX0Lz9x99eIo5/eBuNaF8I33BWOJZTb/MckaGbxqxmAeUw== X-Received: by 10.28.11.204 with SMTP id 195mr2126340wml.132.1504440554553; Sun, 03 Sep 2017 05:09:14 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, kernel-hardening@lists.openwall.com Cc: Ard Biesheuvel , Arnd Bergmann , Nicolas Pitre , Russell King , Kees Cook , Thomas Garnier , Marc Zyngier , Mark Rutland , Tony Lindgren , Matt Fleming , Dave Martin Date: Sun, 3 Sep 2017 13:07:46 +0100 Message-Id: <20170903120757.14968-19-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170903120757.14968-1-ard.biesheuvel@linaro.org> References: <20170903120757.14968-1-ard.biesheuvel@linaro.org> Subject: [kernel-hardening] [PATCH v2 18/29] arm-soc: tegra: make sleep asm code runtime relocatable X-Virus-Scanned: ClamAV using ClamSMTP The PIE kernel build does not allow absolute references encoded in movw/movt instruction pairs, so use our mov_l macro instead (which will still use such a pair unless CONFIG_RELOCATABLE is defined) Also, avoid 32-bit absolute literals to refer to absolute symbols. Instead, use a 16 bit reference so that PIE linker cannot get confused whether the symbol reference is subject to relocation at runtime. Signed-off-by: Ard Biesheuvel --- arch/arm/mach-tegra/sleep-tegra20.S | 22 ++++++++++++-------- arch/arm/mach-tegra/sleep-tegra30.S | 6 +++--- arch/arm/mach-tegra/sleep.S | 4 ++-- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 5c8e638ee51a..cab95de5c8f1 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -99,7 +99,7 @@ ENTRY(tegra20_cpu_shutdown) cmp r0, #0 reteq lr @ must not be called for CPU 0 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset + ldrh r2, 0f mov r12, #CPU_RESETTABLE strb r12, [r1, r2] @@ -121,6 +121,7 @@ ENTRY(tegra20_cpu_shutdown) beq . ret lr ENDPROC(tegra20_cpu_shutdown) +0: .short __tegra20_cpu1_resettable_status_offset #endif #ifdef CONFIG_PM_SLEEP @@ -181,6 +182,9 @@ ENTRY(tegra_pen_unlock) ret lr ENDPROC(tegra_pen_unlock) +.L__tegra20_cpu1_resettable_status_offset: + .short __tegra20_cpu1_resettable_status_offset + /* * tegra20_cpu_clear_resettable(void) * @@ -189,7 +193,7 @@ ENDPROC(tegra_pen_unlock) */ ENTRY(tegra20_cpu_clear_resettable) mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset + ldrh r2, .L__tegra20_cpu1_resettable_status_offset mov r12, #CPU_NOT_RESETTABLE strb r12, [r1, r2] ret lr @@ -203,7 +207,7 @@ ENDPROC(tegra20_cpu_clear_resettable) */ ENTRY(tegra20_cpu_set_resettable_soon) mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset + ldrh r2, .L__tegra20_cpu1_resettable_status_offset mov r12, #CPU_RESETTABLE_SOON strb r12, [r1, r2] ret lr @@ -217,7 +221,7 @@ ENDPROC(tegra20_cpu_set_resettable_soon) */ ENTRY(tegra20_cpu_is_resettable_soon) mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset + ldrh r2, .L__tegra20_cpu1_resettable_status_offset ldrb r12, [r1, r2] cmp r12, #CPU_RESETTABLE_SOON moveq r0, #1 @@ -238,11 +242,11 @@ ENTRY(tegra20_sleep_core_finish) bl tegra_disable_clean_inv_dcache mov r0, r4 - mov32 r3, tegra_shut_off_mmu + mov_l r3, tegra_shut_off_mmu add r3, r3, r0 - mov32 r0, tegra20_tear_down_core - mov32 r1, tegra20_iram_start + mov_l r0, tegra20_tear_down_core + mov_l r1, tegra20_iram_start sub r0, r0, r1 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA add r0, r0, r1 @@ -265,7 +269,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) bl tegra_disable_clean_inv_dcache mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset + ldrh r4, .L__tegra20_cpu1_resettable_status_offset mov r3, #CPU_RESETTABLE strb r3, [r0, r4] @@ -284,7 +288,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) bl tegra_pen_lock mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset + ldrh r4, .L__tegra20_cpu1_resettable_status_offset mov r3, #CPU_NOT_RESETTABLE strb r3, [r0, r4] diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index dd4a67dabd91..478b2ca3ef6e 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -261,11 +261,11 @@ ENTRY(tegra30_sleep_core_finish) mov32 r6, TEGRA_FLOW_CTRL_BASE mov32 r7, TEGRA_TMRUS_BASE - mov32 r3, tegra_shut_off_mmu + mov_l r3, tegra_shut_off_mmu add r3, r3, r0 - mov32 r0, tegra30_tear_down_core - mov32 r1, tegra30_iram_start + mov_l r0, tegra30_tear_down_core + mov_l r1, tegra30_iram_start sub r0, r0, r1 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA add r0, r0, r1 diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 5e3496753df1..785df3edc767 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -101,11 +101,11 @@ ENTRY(tegra_sleep_cpu_finish) bl tegra_disable_clean_inv_dcache mov r0, r4 - mov32 r6, tegra_tear_down_cpu + mov_l r6, tegra_tear_down_cpu ldr r1, [r6] add r1, r1, r0 - mov32 r3, tegra_shut_off_mmu + mov_l r3, tegra_shut_off_mmu add r3, r3, r0 mov r0, r1