From patchwork Tue May 29 22:15:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10437291 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D180601C7 for ; Tue, 29 May 2018 22:20:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 042832890F for ; Tue, 29 May 2018 22:20:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E9B542891F; Tue, 29 May 2018 22:20:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 169462890F for ; Tue, 29 May 2018 22:20:01 +0000 (UTC) Received: (qmail 17897 invoked by uid 550); 29 May 2018 22:17:22 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 17732 invoked from network); 29 May 2018 22:17:19 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jr9rqOr1PZ+yIQGKxWCfmSgqjlwc9GIkWYNzlLym9+0=; b=v455hkKnT9dmSUOjcaN3sLGwC3J8u9cpnw1d5MsJe5oGuClRCQ8cE6kb7WBNjZ7VRM 9TiOvcPZIQvr1YIzzN9XKOfo4qbZPY/MRQZmJmVixn6947BDJ8nBwHn6jomTTHjxoUDe 3GOZEcF978bQSM9EE1fOpO/mtpOKYyx5m+ebDC9ZZwV7q8g1YuXGTu7j8QPkLrNYjUtG wsgxqjZmQTZCa3b+FfafCTdXesi0Iz1yBIs3WKJen9bjtuXWG57l6OnBNah5CyBiZ0Cg PVmR6KoPDzzVeSo09YNfrnvenX6FW8IMy22iDgevQvu4x6vjaIzvRq97HVcjUuhCE1Oo 5AvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jr9rqOr1PZ+yIQGKxWCfmSgqjlwc9GIkWYNzlLym9+0=; b=nHIYtfq6OYWCw2ztv52eM6QLVApu2wYefZ6K6UmOSSYfaIh1s8qtJz0WWrN6a9Mlnu NjixiDF/YQRrSXR+HAlVWVKcNLlWBKFw1l87/+EXTp4OoxYGcdIrepfVUbPcURuFM8p7 gdc01KAOiY89cuSUyO5KkUpAGjKvDjIXX7dJMoXiSCyUdLjTEcRz7XrDAN+g65OdEeKk oBpYM1BVLXDzSHoADXLlynZB1t8hYB2/VJfQY9RmZtrkBL17PUvckrJF72vDnAK+AsUD VlVqmcmrLpzN9/+TO5whAQXvJbMDELyKHoA3nbz7BDtYw00JKYKnEIIkDMiSxj6wEdhM CDtg== X-Gm-Message-State: ALKqPwdM+L7CIPxbKJV/Uqkjff7I2B497fBJBgnsTbL0gybLa3xRVW/Q aLCwW4L2Zz+r1bswbKewvP5J8hb1mLs= X-Google-Smtp-Source: ADUXVKKLOOO9X1g4xJI4iw04Z3ZsFAqIrPsfrOdSyhKN/glG9LPEiBvyU1ITa/eyKzSOurHRajBOHg== X-Received: by 2002:a17:902:8a81:: with SMTP id p1-v6mr225319plo.33.1527632226926; Tue, 29 May 2018 15:17:06 -0700 (PDT) From: Thomas Garnier To: kernel-hardening@lists.openwall.com Cc: Thomas Garnier , Juergen Gross , Alok Kataria , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, virtualization@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 12/27] x86/paravirt: Adapt assembly for PIE support Date: Tue, 29 May 2018 15:15:13 -0700 Message-Id: <20180529221625.33541-13-thgarnie@google.com> X-Mailer: git-send-email 2.17.0.921.gf22659ad46-goog In-Reply-To: <20180529221625.33541-1-thgarnie@google.com> References: <20180529221625.33541-1-thgarnie@google.com> X-Virus-Scanned: ClamAV using ClamSMTP if PIE is enabled, switch the paravirt assembly constraints to be compatible. The %c/i constrains generate smaller code so is kept by default. Position Independent Executable (PIE) support will allow to extend the KASLR randomization range 0xffffffff80000000. Signed-off-by: Thomas Garnier --- arch/x86/include/asm/paravirt_types.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 180bc0bff0fb..140747a98d94 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -337,9 +337,17 @@ extern struct pv_lock_ops pv_lock_ops; #define PARAVIRT_PATCH(x) \ (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) +#ifdef CONFIG_X86_PIE +#define paravirt_opptr_call "a" +#define paravirt_opptr_type "p" +#else +#define paravirt_opptr_call "c" +#define paravirt_opptr_type "i" +#endif + #define paravirt_type(op) \ [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ - [paravirt_opptr] "i" (&(op)) + [paravirt_opptr] paravirt_opptr_type (&(op)) #define paravirt_clobber(clobber) \ [paravirt_clobber] "i" (clobber) @@ -395,7 +403,7 @@ int paravirt_disable_iospace(void); */ #define PARAVIRT_CALL \ ANNOTATE_RETPOLINE_SAFE \ - "call *%c[paravirt_opptr];" + "call *%" paravirt_opptr_call "[paravirt_opptr];" /* * These macros are intended to wrap calls through one of the paravirt