From patchwork Tue May 29 22:15:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10437275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D8907601E9 for ; Tue, 29 May 2018 22:18:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0A342890F for ; Tue, 29 May 2018 22:18:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B54682891B; Tue, 29 May 2018 22:18:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id F128E2890F for ; Tue, 29 May 2018 22:18:56 +0000 (UTC) Received: (qmail 16367 invoked by uid 550); 29 May 2018 22:17:04 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 16234 invoked from network); 29 May 2018 22:16:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Qg1ESe27k6SOY1ZSCxe9uGhLdCjJoap2KMfXHyL1mhw=; b=TIStLCd5XCQ+tgoXdadFvLyjmzsthWIru0MPWsGpv5f4VF1PT0accD79/rb0sPiPdi YvhX06nJwUdnJzRigbb/9E5yBkyeNIpsoO2dQWiESdnBj6i8sm0IB9tl6zZ2HW6VDwos yZC4zq14wECPOXWuvdy8QcPXtoZo3LAHShBhP+BSQxCoW9R06Lh1wgpoFU2VuZxMDI82 sUoLZuoB9RZMRr6GV6ZokEQ+MhH3CdSbGM7xWO4cjwHX80PTwg+Aq96vCF+9ncl3c8QA yR95GMXdVieSqvFpsmWWP66fZ0xhcT8lt9ygUNPEYfP9bsP4emPtqh2qEQz/2gs0rX3u Gf0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Qg1ESe27k6SOY1ZSCxe9uGhLdCjJoap2KMfXHyL1mhw=; b=MrRDEuUAtfJ9n61TFoZLled0PyJnJl5GcW/4dcsq1PILCQ2falZdMF+k792gIJKq4E ZfIzE15xEWClGQGYmQiaUsr226EVG4qE6MQQG1wt3jVNS/7QR/fH1rTr9MeODD4dAYJ4 mg/SY6xM355cJ5dslgac3vt/tOzLgY0gJd8+Ch4GmS8Gat07ZzLivHU+7TtZRcGnotcQ 4bJU+RlNTv2Xf0DkKF7d6sml/XEgW/ZGYlqFbZMq5k51aBE5ts7U8xR35GOXj75pCH+R 4elconnGAvJy5zKC/D0PtT4SZ/7uuNfKgxmTT5JVrd7NAhU/K90JUj2ieoxo+j5BfKer qYrg== X-Gm-Message-State: ALKqPwc6ufrH2JUQ1D5FnzDZj8ayGevAdN8zGQ7yS/XAQ4qsnTVS6moH cc2u6BQo+UZmWfqH8xgUZcLJGA4JPrA= X-Google-Smtp-Source: ADUXVKIm+JwmqDDPN0aS9nBIZ0mQV8xxm8beahFGZT2RIVjMiznmh8UoErNeK6/TOanWtwVDsUTjEg== X-Received: by 2002:a17:902:ab8d:: with SMTP id f13-v6mr217693plr.81.1527632206631; Tue, 29 May 2018 15:16:46 -0700 (PDT) From: Thomas Garnier To: kernel-hardening@lists.openwall.com Cc: Thomas Garnier , Skip Kees Cook , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Josh Poimboeuf , Arnaldo Carvalho de Melo , Andrey Ryabinin , Greg Kroah-Hartman , linux-kernel@vger.kernel.org Subject: [PATCH v4 04/27] x86: Add macro to get symbol address for PIE support Date: Tue, 29 May 2018 15:15:05 -0700 Message-Id: <20180529221625.33541-5-thgarnie@google.com> X-Mailer: git-send-email 2.17.0.921.gf22659ad46-goog In-Reply-To: <20180529221625.33541-1-thgarnie@google.com> References: <20180529221625.33541-1-thgarnie@google.com> X-Virus-Scanned: ClamAV using ClamSMTP Add a new _ASM_MOVABS macro to fetch a symbol address. It will be used to replace "_ASM_MOV $, %dst" code construct that are not compatible with PIE. Signed-off-by: Thomas Garnier --- arch/x86/include/asm/asm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h index 219faaec51df..4492a35fad69 100644 --- a/arch/x86/include/asm/asm.h +++ b/arch/x86/include/asm/asm.h @@ -30,6 +30,7 @@ #define _ASM_ALIGN __ASM_SEL(.balign 4, .balign 8) #define _ASM_MOV __ASM_SIZE(mov) +#define _ASM_MOVABS __ASM_SEL(movl, movabsq) #define _ASM_INC __ASM_SIZE(inc) #define _ASM_DEC __ASM_SIZE(dec) #define _ASM_ADD __ASM_SIZE(add)