From patchwork Tue May 29 22:15:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10437287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3DF84601C7 for ; Tue, 29 May 2018 22:19:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 275462890F for ; Tue, 29 May 2018 22:19:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1BBF32891F; Tue, 29 May 2018 22:19:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 3D2F52890F for ; Tue, 29 May 2018 22:19:49 +0000 (UTC) Received: (qmail 17828 invoked by uid 550); 29 May 2018 22:17:21 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 17542 invoked from network); 29 May 2018 22:17:11 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cKt2G9+eolPSqAr/ykO9awNJAZzUjST+sKgFyQlFtVg=; b=gVmHnopc1aEY5SZMPxAkbtCn+sHwTHenonzg+ZAV9z2dsA78kmcpVce9KS8O71LrHJ Rq4xKOHBsX18v8LNy/RnJYm21v5bfJ2BQLBqa3IN8k1Wh5Q1UH27QhLbQSPr3x1EYO+7 xxCIqxk9ApU6wuPGQ7VTsIdl2E50W6HkGTg/RsOc19pXDeYs/OiciOL4sE1P0kEhNn6l AnAfpVf4wKhcSTCdiiz+tdQHHHqCw5dE+0wsOuxA6tbCNYTEudRu1Qp5G2smRdAYPkBL bBudcXYX59aknt72OwYCTiA0bHXjzZ+Fbb2h4b7BNeJQX7A+M68e2n89aRcC/KGa85WO 8SkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cKt2G9+eolPSqAr/ykO9awNJAZzUjST+sKgFyQlFtVg=; b=BiwOJfy2k5dSBfSM/e26JfeKImaZ9NF5cDzfzu50wavheopUBpqAOiNw/KfnB+UN3O 3ZfKxlqMCHDPX97IgJhi+3f3UMDy0GNCcikXuCupJRhp2tMyxekYVk5jyWFhdWPgP2+A UEsmg3LfZyGFKQcR/O30pMT4TI8BoJZXootqQ+hXtrW3psPUMATlnvhS3+mVesafZrjr UBNO3rNtKJLEuxtRI0uKwgF8uTjfDOVqMATvson5kGROcaI9SM6D0m2UHYtIF025SULk 0jCPvTozixWNE1Yon2tP/OEn42V02ttS0so0ALEKrctZ9hLMqvBhXz9cX9JV/ui/gd1j ozmg== X-Gm-Message-State: ALKqPwe3UZhERxmSVxIW1b2EjUv0EwyO4+Wvttm1IgGmYoua8U2j6HTY zgwHJ/lBsw/iSsKQAtHiBy0/y3o1QD4= X-Google-Smtp-Source: ADUXVKJjb0iqr+HMS0GIphd6kFkG2x7aHF+z2oTTay9/RJXccJj4nMr/1DOSuhBXCpDOaiCLfSBhVQ== X-Received: by 2002:a17:902:2f84:: with SMTP id t4-v6mr251643plb.24.1527632219724; Tue, 29 May 2018 15:16:59 -0700 (PDT) From: Thomas Garnier To: kernel-hardening@lists.openwall.com Cc: Thomas Garnier , "Skip Kirill A. Shutemov" , Skip Vitaly Kuznetsov , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Borislav Petkov , Andy Lutomirski , linux-kernel@vger.kernel.org Subject: [PATCH v4 08/27] x86/CPU: Adapt assembly for PIE support Date: Tue, 29 May 2018 15:15:09 -0700 Message-Id: <20180529221625.33541-9-thgarnie@google.com> X-Mailer: git-send-email 2.17.0.921.gf22659ad46-goog In-Reply-To: <20180529221625.33541-1-thgarnie@google.com> References: <20180529221625.33541-1-thgarnie@google.com> X-Virus-Scanned: ClamAV using ClamSMTP Change the assembly code to use only relative references of symbols for the kernel to be PIE compatible. Use the new _ASM_MOVABS macro instead of the 'mov $symbol, %dst' construct. Position Independent Executable (PIE) support will allow to extend the KASLR randomization range 0xffffffff80000000. Signed-off-by: Thomas Garnier --- arch/x86/include/asm/processor.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index e28add6b791f..7ae9fb91f7b5 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -50,7 +50,7 @@ static inline void *current_text_addr(void) { void *pc; - asm volatile("mov $1f, %0; 1:":"=r" (pc)); + asm volatile(_ASM_MOVABS " $1f, %0; 1:":"=r" (pc)); return pc; } @@ -711,6 +711,7 @@ static inline void sync_core(void) : ASM_CALL_CONSTRAINT : : "memory"); #else unsigned int tmp; + unsigned long tmp2; asm volatile ( UNWIND_HINT_SAVE @@ -721,11 +722,13 @@ static inline void sync_core(void) "pushfq\n\t" "mov %%cs, %0\n\t" "pushq %q0\n\t" - "pushq $1f\n\t" + "leaq 1f(%%rip), %1\n\t" + "pushq %1\n\t" "iretq\n\t" UNWIND_HINT_RESTORE "1:" - : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); + : "=&r" (tmp), "=&r" (tmp2), ASM_CALL_CONSTRAINT + : : "cc", "memory"); #endif }