From patchwork Mon Jun 25 22:39:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10488299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 245B7601A0 for ; Tue, 26 Jun 2018 08:43:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F25D287DC for ; Tue, 26 Jun 2018 08:43:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03D5B287E2; Tue, 26 Jun 2018 08:43:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id E428A287DC for ; Tue, 26 Jun 2018 08:43:48 +0000 (UTC) Received: (qmail 28008 invoked by uid 550); 26 Jun 2018 08:39:50 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Delivered-To: moderator for kernel-hardening@lists.openwall.com Received: (qmail 11945 invoked from network); 25 Jun 2018 22:42:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:date:in-reply-to:message-id:references:subject:from:to :cc; bh=3sO3Q0vr9WbfC6HW1jNT+fUgdjvmwWTyo2KWl50eZ0U=; b=Drt2PMwXDWzZjPXqxbzC1JyyBsLcTXiVt5iWjNbAonuIG29fnjMioTgbjbjgoPjROQ jFU4xt0ont+NjCvhft2kreTjGemKGR8FIjDRkRNqNPy8JSCLEDxGzfGJK0yQa6VH+w4s pUU+Lb7LKLlGx96ogsf7R/PAfNU6zIG1IUP8+0DPyytFWlyp/P6zevL4hwbfJwGdq9n/ a4ddhGMqT+TB5K6m/zZFnljfU3oKNuNeMbPmg1rEc4xbZoEWJTzbtpz5WrjFSZVPp61C KxowY7LiEIuTf02ZysGS9Lb02HAoI3M32EzsiqlbOYwIMxUj/2zLUpNSEuJaFgTYOySv rXDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:date:in-reply-to:message-id :references:subject:from:to:cc; bh=3sO3Q0vr9WbfC6HW1jNT+fUgdjvmwWTyo2KWl50eZ0U=; b=cKZ5G92ddcsEcOvR9+0HlIss5G2JDdB78D1bpYnym8JSpQo6w5YCK/JK/YyeXWQA62 /8Jz32FMrP5hDcMbiWItGhQ/KbmLTZAbLCEgky/FqJjU/4SwJ1kt9mNRVXhhHJKrthDJ RTXskpUhyZjIt6xeGDueaurSgS98SesTNQWFTwU2yCtBHx6VmaznZBpjKVy597q3vh8C TGQzg6aZkT2Npmd6Je3GwNGIe9E84AnJmtRE7QHZPorE0vEZHcf5R+bfe+f6Ky7Uy872 fHPtS2VIQaY7hnghJNhmdqjBvrd5GKO7T4uiJSBU6bj/R/sNKNQKKaSx/QXbn610Xk6O 3ipg== X-Gm-Message-State: APt69E31JoCxQxZqvS7IQ0bJR6Cgu/UZrOw6wnFDmXMdL5NiCD2ZRd2o G8rz03VfrlHO9/Bl+nQZCj671KVf2eIEqOWEl/FYDfO8+AihUkEku8vPjE25kvdrpoD0FW/se1s ae0q9OA2p3otvI6zcYrCzSyEES/sNaxdhqq5Nw+/jMySKNrcqvQ8xV6reld/r/mUdA+HDWAUoDk PJJTcwVCxm X-Google-Smtp-Source: ADUXVKInhT/3s9jKv8pd8LikYjtOUNIFDTJI1nTeXRVH64jgbER4G1M6Ewxsn4+YD0QHiaXv7MRWmuRvlS/a1A== MIME-Version: 1.0 X-Received: by 2002:ac8:29b7:: with SMTP id 52-v6mr3203880qts.6.1529966525900; Mon, 25 Jun 2018 15:42:05 -0700 (PDT) Date: Mon, 25 Jun 2018 15:39:06 -0700 In-Reply-To: <20180625224014.134829-1-thgarnie@google.com> Message-Id: <20180625224014.134829-19-thgarnie@google.com> References: <20180625224014.134829-1-thgarnie@google.com> X-Mailer: git-send-email 2.18.0.rc2.346.g013aa6912e-goog Subject: [PATCH v5 18/27] xen: Adapt assembly for PIE support From: Thomas Garnier To: kernel-hardening@lists.openwall.com Cc: Thomas Garnier , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Boris Ostrovsky , Juergen Gross , Philippe Ombredanne , Greg Kroah-Hartman , Kate Stewart , "H.J. Lu" , linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org X-Virus-Scanned: ClamAV using ClamSMTP Change the assembly code to use the new _ASM_MOVABS macro which get a symbol reference while being PIE compatible. Adapt the relocation tool to ignore 32-bit Xen code. Position Independent Executable (PIE) support will allow to extend the KASLR randomization range 0xffffffff80000000. Signed-off-by: Thomas Garnier Reviewed-by: Juergen Gross --- arch/x86/tools/relocs.c | 16 +++++++++++++++- arch/x86/xen/xen-head.S | 11 ++++++----- arch/x86/xen/xen-pvh.S | 14 ++++++++++---- 3 files changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c index a35cc337f883..29283ad3950f 100644 --- a/arch/x86/tools/relocs.c +++ b/arch/x86/tools/relocs.c @@ -832,6 +832,16 @@ static int is_percpu_sym(ElfW(Sym) *sym, const char *symname) strncmp(symname, "init_per_cpu_", 13); } +/* + * Check if the 32-bit relocation is within the xenpvh 32-bit code. + * If so, ignores it. + */ +static int is_in_xenpvh_assembly(ElfW(Addr) offset) +{ + ElfW(Sym) *sym = sym_lookup("pvh_start_xen"); + return sym && (offset >= sym->st_value) && + (offset < (sym->st_value + sym->st_size)); +} static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, const char *symname) @@ -895,8 +905,12 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, * the relocations are processed. * Make sure that the offset will fit. */ - if (r_type != R_X86_64_64 && (int32_t)offset != (int64_t)offset) + if (r_type != R_X86_64_64 && + (int32_t)offset != (int64_t)offset) { + if (is_in_xenpvh_assembly(offset)) + break; die("Relocation offset doesn't fit in 32 bits\n"); + } if (r_type == R_X86_64_64) add_reloc(&relocs64, offset); diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 5077ead5e59c..4418ff0a1d96 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -28,14 +28,15 @@ ENTRY(startup_xen) /* Clear .bss */ xor %eax,%eax - mov $__bss_start, %_ASM_DI - mov $__bss_stop, %_ASM_CX + _ASM_MOVABS $__bss_start, %_ASM_DI + _ASM_MOVABS $__bss_stop, %_ASM_CX sub %_ASM_DI, %_ASM_CX shr $__ASM_SEL(2, 3), %_ASM_CX rep __ASM_SIZE(stos) - mov %_ASM_SI, xen_start_info - mov $init_thread_union+THREAD_SIZE, %_ASM_SP + _ASM_MOVABS $xen_start_info, %_ASM_AX + _ASM_MOV %_ASM_SI, (%_ASM_AX) + _ASM_MOVABS $init_thread_union+THREAD_SIZE, %_ASM_SP #ifdef CONFIG_X86_64 /* Set up %gs. @@ -46,7 +47,7 @@ ENTRY(startup_xen) * init data section till per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movq $INIT_PER_CPU_VAR(irq_stack_union),%rax + movabsq $INIT_PER_CPU_VAR(irq_stack_union),%rax cdq wrmsr #endif diff --git a/arch/x86/xen/xen-pvh.S b/arch/x86/xen/xen-pvh.S index ca2d3b2bf2af..4b83f861b655 100644 --- a/arch/x86/xen/xen-pvh.S +++ b/arch/x86/xen/xen-pvh.S @@ -114,8 +114,8 @@ ENTRY(pvh_start_xen) call xen_prepare_pvh /* startup_64 expects boot_params in %rsi. */ - mov $_pa(pvh_bootparams), %rsi - mov $_pa(startup_64), %rax + movabs $_pa(pvh_bootparams), %rsi + movabs $_pa(startup_64), %rax jmp *%rax #else /* CONFIG_X86_64 */ @@ -161,10 +161,16 @@ END(pvh_start_xen) .section ".init.data","aw" .balign 8 + /* + * Use an ASM_PTR (quad on x64) for _pa(gdt_start) because PIE requires + * a pointer size storage value before applying the relocation. On + * 32-bit _ASM_PTR will be a long which is aligned the space needed for + * relocation. + */ gdt: .word gdt_end - gdt_start - .long _pa(gdt_start) - .word 0 + _ASM_PTR _pa(gdt_start) + .balign 8 gdt_start: .quad 0x0000000000000000 /* NULL descriptor */ #ifdef CONFIG_X86_64