From patchwork Thu Jan 31 19:24:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 10791357 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3C8A1390 for ; Thu, 31 Jan 2019 19:45:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9BF3E3102E for ; Thu, 31 Jan 2019 19:45:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F54631793; Thu, 31 Jan 2019 19:45:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 763133102E for ; Thu, 31 Jan 2019 19:45:17 +0000 (UTC) Received: (qmail 12239 invoked by uid 550); 31 Jan 2019 19:43:52 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Delivered-To: moderator for kernel-hardening@lists.openwall.com Received: (qmail 20267 invoked from network); 31 Jan 2019 19:29:12 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ev8JPAf+GoLzOHws3FGQ46h+PQ2kpPn+0k5OrkzIAiY=; b=UGN68F6ZcLmOxFwtzgS7fsHrX5YxpIwlbBo6TP7Fu9IW9TkcJwup0pITpRMnT+nuDf w4uVcT3v7EO3VxAHFUNjGW+EnaOJTtgrWJXaaq86yPeAy8pj6KU8MV8M8h5PqTGfo9ga 2/GbaYCZllZLW9JbM9nvcbFpNgpUUiyzG27bA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ev8JPAf+GoLzOHws3FGQ46h+PQ2kpPn+0k5OrkzIAiY=; b=ja49rdqw5KDTBhh1cwV/kn2auEvyufvyBusCqo3uCG0Vc3OdOgS5EV4gBYC2o4dRER 5rYy6fbIq+Xkpiib96UxWGrNjPz0nn2KNErERMksd/bqG3lIU5U7Qua5As5gtCuA/glS ErjWdjKNnxeomwpIHBtiV0t+hqdWgStskMGeRdipsqbT7bRe8GI04HEVzv/+wIQfxoMc VPf2hSTGKgClQAtGd7aA1t9Kf9WNLxufIAbWGAWV9OHK4/jkjOfs7/zG66D2PMJIyh6c mgWJwtgdVFw2JmVu3KzRteZz6On6iOqC1IiD1DkSYMg2Z69Xz0sgNH3GSBHmKQ5Mo/Jw oR/g== X-Gm-Message-State: AJcUukecstDp0FvjCnFIUnPLiTf+0dXRegzLdOfGPiWepKxPWBQ8XV2T DF1Djd+6iNM9eh1WdRbaYBedvCMxpjI= X-Google-Smtp-Source: ALg8bN4NDirLuK4HzuFomYq8ZzIZ6jTLOGbE6YQz67HSslDD7eHHzc2BLBM7I6v0SC+n1ZYpkGgPIw== X-Received: by 2002:a62:1f9d:: with SMTP id l29mr36074865pfj.14.1548962940145; Thu, 31 Jan 2019 11:29:00 -0800 (PST) From: Thomas Garnier To: kernel-hardening@lists.openwall.com Cc: kristen@linux.intel.com, Thomas Garnier , Juergen Gross , Boris Ostrovsky , Stefano Stabellini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, Thomas Garnier , Ard Biesheuvel , Joerg Roedel , "H.J. Lu" , Jordan Borgner , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 18/27] xen: Adapt assembly for PIE support Date: Thu, 31 Jan 2019 11:24:25 -0800 Message-Id: <20190131192533.34130-19-thgarnie@chromium.org> X-Mailer: git-send-email 2.20.1.495.gaa96b0ce6b-goog In-Reply-To: <20190131192533.34130-1-thgarnie@chromium.org> References: <20190131192533.34130-1-thgarnie@chromium.org> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Change the assembly code to use the new _ASM_MOVABS macro which get a symbol reference while being PIE compatible. Adapt the relocation tool to ignore 32-bit Xen code. Position Independent Executable (PIE) support will allow to extend the KASLR randomization range below 0xffffffff80000000. Signed-off-by: Thomas Garnier Reviewed-by: Juergen Gross --- arch/x86/platform/pvh/head.S | 14 ++++++++++---- arch/x86/tools/relocs.c | 16 +++++++++++++++- arch/x86/xen/xen-head.S | 11 ++++++----- 3 files changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/x86/platform/pvh/head.S b/arch/x86/platform/pvh/head.S index 1f8825bbaffb..e52d8b31e01d 100644 --- a/arch/x86/platform/pvh/head.S +++ b/arch/x86/platform/pvh/head.S @@ -103,8 +103,8 @@ ENTRY(pvh_start_xen) call xen_prepare_pvh /* startup_64 expects boot_params in %rsi. */ - mov $_pa(pvh_bootparams), %rsi - mov $_pa(startup_64), %rax + movabs $_pa(pvh_bootparams), %rsi + movabs $_pa(startup_64), %rax jmp *%rax #else /* CONFIG_X86_64 */ @@ -150,10 +150,16 @@ END(pvh_start_xen) .section ".init.data","aw" .balign 8 + /* + * Use an ASM_PTR (quad on x64) for _pa(gdt_start) because PIE requires + * a pointer size storage value before applying the relocation. On + * 32-bit _ASM_PTR will be a long which is aligned the space needed for + * relocation. + */ gdt: .word gdt_end - gdt_start - .long _pa(gdt_start) - .word 0 + _ASM_PTR _pa(gdt_start) + .balign 8 gdt_start: .quad 0x0000000000000000 /* NULL descriptor */ #ifdef CONFIG_X86_64 diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c index 2a3c703218cc..1b5ee38446b6 100644 --- a/arch/x86/tools/relocs.c +++ b/arch/x86/tools/relocs.c @@ -837,6 +837,16 @@ static int is_percpu_sym(ElfW(Sym) *sym, const char *symname) strncmp(symname, "init_per_cpu_", 13); } +/* + * Check if the 32-bit relocation is within the xenpvh 32-bit code. + * If so, ignores it. + */ +static int is_in_xenpvh_assembly(Elf_Addr offset) +{ + Elf_Sym *sym = sym_lookup("pvh_start_xen"); + return sym && (offset >= sym->st_value) && + (offset < (sym->st_value + sym->st_size)); +} static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, const char *symname) @@ -909,8 +919,12 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym, * the relocations are processed. * Make sure that the offset will fit. */ - if (r_type != R_X86_64_64 && (int32_t)offset != (int64_t)offset) + if (r_type != R_X86_64_64 && + (int32_t)offset != (int64_t)offset) { + if (is_in_xenpvh_assembly(offset)) + break; die("Relocation offset doesn't fit in 32 bits\n"); + } if (r_type == R_X86_64_64) add_reloc(&relocs64, offset); diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 5077ead5e59c..4418ff0a1d96 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -28,14 +28,15 @@ ENTRY(startup_xen) /* Clear .bss */ xor %eax,%eax - mov $__bss_start, %_ASM_DI - mov $__bss_stop, %_ASM_CX + _ASM_MOVABS $__bss_start, %_ASM_DI + _ASM_MOVABS $__bss_stop, %_ASM_CX sub %_ASM_DI, %_ASM_CX shr $__ASM_SEL(2, 3), %_ASM_CX rep __ASM_SIZE(stos) - mov %_ASM_SI, xen_start_info - mov $init_thread_union+THREAD_SIZE, %_ASM_SP + _ASM_MOVABS $xen_start_info, %_ASM_AX + _ASM_MOV %_ASM_SI, (%_ASM_AX) + _ASM_MOVABS $init_thread_union+THREAD_SIZE, %_ASM_SP #ifdef CONFIG_X86_64 /* Set up %gs. @@ -46,7 +47,7 @@ ENTRY(startup_xen) * init data section till per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movq $INIT_PER_CPU_VAR(irq_stack_union),%rax + movabsq $INIT_PER_CPU_VAR(irq_stack_union),%rax cdq wrmsr #endif