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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD80.mail.protection.outlook.com (10.167.244.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:29 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:27 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 0/9] misc: Add AMD side band interface(SBI) functionality Date: Thu, 12 Sep 2024 07:08:01 +0000 Message-ID: <20240912070810.1644621-1-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD80:EE_|PH7PR12MB6955:EE_ X-MS-Office365-Filtering-Correlation-Id: dfcc5cf6-65df-4c6a-0001-08dcd2f9b4b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:29.9240 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfcc5cf6-65df-4c6a-0001-08dcd2f9b4b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD80.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6955 AMD's Advanced Platform Management Link (APML) interface provides system management functionality accessed by the baseboard management controller (BMC). sbrmi driver under hwmon subsystem, which is probed as an i2c driver and reports power using APML specified protocol. However, APML interface defines few other protocols to support full system management functionality out-of-band. Out-of-band management is term used for BMC talking to system management unit (IP in the processor). AMD's documentation called this link as side band interface. This patchset is an attempt to add all APML core functionality in one place and provide hwmon and user space interface 1. [Patch 1] Move the i2c client probe, hwmon sensors and sbrmi core functionality from drivers/hwmon to drivers/misc/ 2. [Patch 2] Convert i2c to regmap which provides multiple benefits over direct smbus APIs. a. i2c/i3c support and b. 1 byte/2 byte RMI register size addressing 3. [Patch 3] Optimize wait condition with regmap API regmap_read_poll_timeout as per suggestion from Arnd 4. [Patch 4, 5] Register a misc device which provides a. An ioctl interface through node /dev/sbrmiX b. Register sets is common across APML protocols. IOCTL is providing synchronization among protocols as transactions may create race condition. 5. [Subsequent patches 6, 7 and 8] add support for AMD custom protocols a. CPUID b. MCAMSR c. Register xfer 6. [Patch 9] AMD side band description document Open-sourced and widely used https://github.com/amd/esmi_oob_library will continue to provide user-space programmable API. Akshay Gupta (9): hwmon/misc: amd-sbi: Move core sbrmi from hwmon to misc misc: amd-sbi: Use regmap subsystem misc: amd-sbi: Optimize the wait condition for mailbox command completion misc: amd-sbi: Add support for AMD_SBI IOCTL misc: amd-sbi: Add support for mailbox error codes misc: amd-sbi: Add support for CPUID protocol misc: amd-sbi: Add support for MCA register protocol misc: amd-sbi: Add supoort for register xfer misc: amd-sbi: Add document for AMD SB IOCTL description Documentation/misc-devices/amd-sbi.rst | 84 ++++ Documentation/misc-devices/index.rst | 1 + .../userspace-api/ioctl/ioctl-number.rst | 2 + drivers/hwmon/Kconfig | 10 - drivers/hwmon/sbrmi.c | 357 -------------- drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/amd-sbi/Kconfig | 9 + drivers/misc/amd-sbi/Makefile | 3 + drivers/misc/amd-sbi/rmi-core.c | 452 ++++++++++++++++++ drivers/misc/amd-sbi/rmi-core.h | 67 +++ drivers/misc/amd-sbi/rmi-hwmon.c | 122 +++++ drivers/misc/amd-sbi/rmi-i2c.c | 135 ++++++ include/uapi/misc/amd-apml.h | 97 ++++ 14 files changed, 974 insertions(+), 367 deletions(-) create mode 100644 Documentation/misc-devices/amd-sbi.rst delete mode 100644 drivers/hwmon/sbrmi.c create mode 100644 drivers/misc/amd-sbi/Kconfig create mode 100644 drivers/misc/amd-sbi/Makefile create mode 100644 drivers/misc/amd-sbi/rmi-core.c create mode 100644 drivers/misc/amd-sbi/rmi-core.h create mode 100644 drivers/misc/amd-sbi/rmi-hwmon.c create mode 100644 drivers/misc/amd-sbi/rmi-i2c.c create mode 100644 include/uapi/misc/amd-apml.h