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Received: from 108-223-40-66.lightspeed.sntcca.sbcglobal.net ([108.223.40.66]:35146 helo=localhost) by bh-25.webhostbox.net with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.89) (envelope-from ) id 1dWX0c-002x9s-0v; Sun, 16 Jul 2017 00:02:02 +0000 From: Guenter Roeck To: Hardware Monitoring Cc: Jean Delvare , Guenter Roeck Subject: [PATCH] hwmon: (jc42) Add support for GT30TS00, GT34TS02, and CAT34TS04 Date: Sat, 15 Jul 2017 17:02:00 -0700 Message-Id: <1500163320-26254-1-git-send-email-linux@roeck-us.net> X-Mailer: git-send-email 2.7.4 X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Authenticated-Sender: bh-25.webhostbox.net: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Giantec GT30TS00 GT30TS00 and GT34TS02 as well as ONS CAT34TS04 are used on DDR4 DIMMs. Signed-off-by: Guenter Roeck --- drivers/hwmon/jc42.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c index 1bf22eff0b08..edb6a81a0e10 100644 --- a/drivers/hwmon/jc42.c +++ b/drivers/hwmon/jc42.c @@ -72,6 +72,8 @@ static const unsigned short normal_i2c[] = { #define NXP_MANID 0x1131 /* NXP Semiconductors */ #define ONS_MANID 0x1b09 /* ON Semiconductor */ #define STM_MANID 0x104a /* ST Microelectronics */ +#define GT_MANID 0x1c68 /* Giantec */ +#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ /* Supported chips */ @@ -86,6 +88,13 @@ static const unsigned short normal_i2c[] = { #define AT30TSE004_DEVID 0x2200 #define AT30TSE004_DEVID_MASK 0xffff +/* Giantec */ +#define GT30TS00_DEVID 0x2200 +#define GT30TS00_DEVID_MASK 0xff00 + +#define GT34TS02_DEVID 0x3300 +#define GT34TS02_DEVID_MASK 0xff00 + /* IDT */ #define TSE2004_DEVID 0x2200 #define TSE2004_DEVID_MASK 0xff00 @@ -130,6 +139,9 @@ static const unsigned short normal_i2c[] = { #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ #define CAT6095_DEVID_MASK 0xffe0 +#define CAT34TS04_DEVID 0x2200 +#define CAT34TS04_DEVID_MASK 0xfff0 + /* ST Microelectronics */ #define STTS424_DEVID 0x0101 #define STTS424_DEVID_MASK 0xffff @@ -158,6 +170,8 @@ static struct jc42_chips jc42_chips[] = { { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK }, + { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK }, + { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK }, { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK }, { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK }, @@ -170,6 +184,7 @@ static struct jc42_chips jc42_chips[] = { { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, + { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK }, { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },