@@ -163,6 +163,9 @@
#define M_TACH_UNIT 0x1000
#define INIT_FAN_CTRL 0xFF
+/* How many times we poll the fan_tach controller for rpm data. */
+#define FAN_TACH_RPM_TIMEOUT 25
+
struct aspeed_pwm_tacho_data {
struct regmap *regmap;
unsigned long clk_freq;
@@ -508,7 +511,7 @@ static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
u8 fan_tach_ch)
{
- u32 raw_data, tach_div, clk_source, sec, val;
+ u32 raw_data, tach_div, clk_source, sec, val, timeout;
u8 fan_tach_ch_source, type, mode, both;
regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
@@ -517,12 +520,20 @@ static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
type = priv->pwm_port_type[fan_tach_ch_source];
- sec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
- msleep(sec);
-
regmap_read(priv->regmap, ASPEED_PTCR_RESULT, &val);
- if (!(val & RESULT_STATUS_MASK))
- return -ETIMEDOUT;
+ /*
+ * Instead of sleeping first, poll register for result.
+ * This is based on the reference driver's approach which expects to
+ * receive a value quickly.
+ */
+ timeout = 0;
+ while (!(val & RESULT_STATUS_MASK)) {
+ timeout++;
+ if (timeout > FAN_TACH_RPM_TIMEOUT)
+ return -ETIMEDOUT;
+
+ regmap_read(priv->regmap, ASPEED_PTCR_RESULT, &val);
+ }
raw_data = val & RESULT_VALUE_MASK;
tach_div = priv->type_fan_tach_clock_division[type];
The controller should provide an answer nearly immediately if the fan_tach period is short. I found through testing that the combination of these factors improved the device driver responsiveness. Testing: tested on quanta-q71l board with aspeed ast2400 using a slightly different tree. Signed-off-by: Patrick Venture <venture@google.com> --- drivers/hwmon/aspeed-pwm-tacho.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-)