diff mbox series

[v2,5/9] hwmon/drivers/mr75203: Use HZ macros

Message ID 20210224144222.23762-5-daniel.lezcano@linaro.org (mailing list archive)
State Not Applicable
Headers show
Series None | expand

Commit Message

Daniel Lezcano Feb. 24, 2021, 2:42 p.m. UTC 
HZ unit conversion macros are available in units.h, use them and
remove the duplicate definition.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Christian Eggers <ceggers@arri.de>
---
 drivers/hwmon/mr75203.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Guenter Roeck March 11, 2021, 9:44 p.m. UTC | #1 
On Wed, Feb 24, 2021 at 03:42:15PM +0100, Daniel Lezcano wrote:
> HZ unit conversion macros are available in units.h, use them and
> remove the duplicate definition.

I assume the idea is to submit the series together, so

Acked-by: Guenter Roeck <linux@roeck-us.net>

Guenter

> 
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> Reviewed-by: Christian Eggers <ceggers@arri.de>
> ---
>  drivers/hwmon/mr75203.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
> index 18da5a25e89a..868243dba1ee 100644
> --- a/drivers/hwmon/mr75203.c
> +++ b/drivers/hwmon/mr75203.c
> @@ -17,6 +17,7 @@
>  #include <linux/property.h>
>  #include <linux/regmap.h>
>  #include <linux/reset.h>
> +#include <linux/units.h>
>  
>  /* PVT Common register */
>  #define PVT_IP_CONFIG	0x04
> @@ -37,7 +38,6 @@
>  #define CLK_SYNTH_EN		BIT(24)
>  #define CLK_SYS_CYCLES_MAX	514
>  #define CLK_SYS_CYCLES_MIN	2
> -#define HZ_PER_MHZ		1000000L
>  
>  #define SDIF_DISABLE	0x04
>
diff mbox series

Patch

diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
index 18da5a25e89a..868243dba1ee 100644
--- a/drivers/hwmon/mr75203.c
+++ b/drivers/hwmon/mr75203.c
@@ -17,6 +17,7 @@ 
 #include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
+#include <linux/units.h>
 
 /* PVT Common register */
 #define PVT_IP_CONFIG	0x04
@@ -37,7 +38,6 @@ 
 #define CLK_SYNTH_EN		BIT(24)
 #define CLK_SYS_CYCLES_MAX	514
 #define CLK_SYS_CYCLES_MIN	2
-#define HZ_PER_MHZ		1000000L
 
 #define SDIF_DISABLE	0x04