diff mbox series

[PATCHv2,6/6] arm64: dts: socfpga: add hwmon properties

Message ID 20230508212852.8413-6-dinh.nguyen@linux.intel.com (mailing list archive)
State Changes Requested
Headers show
Series [PATCHv2,1/6] units: add a macro for MILLIVOLT_PER_VOLT | expand

Commit Message

Dinh Nguyen May 8, 2023, 9:28 p.m. UTC 
From: Dinh Nguyen <dinh.nguyen@linux.intel.com>

Add the hardware monitoring properties for Stratix10 and Agilex.

Signed-off-by: Dinh Nguyen <dinh.nguyen@linux.intel.com>
---
v2: add platform specific platforms to DTS files
---
 .../boot/dts/altera/socfpga_stratix10.dtsi    |  4 ++
 .../dts/altera/socfpga_stratix10_socdk.dts    | 31 +++++++++
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  4 ++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex_socdk.dts   | 66 +++++++++++++++++++
 .../dts/intel/socfpga_agilex_socdk_nand.dts   | 66 +++++++++++++++++++
 .../boot/dts/intel/socfpga_n5x_socdk.dts      | 47 +++++++++++++
 7 files changed, 284 insertions(+)

Comments

Krzysztof Kozlowski May 9, 2023, 7:04 a.m. UTC | #1 
On 08/05/2023 23:28, dinh.nguyen@linux.intel.com wrote:
> From: Dinh Nguyen <dinh.nguyen@linux.intel.com>
> 
> Add the hardware monitoring properties for Stratix10 and Agilex.
> 
> Signed-off-by: Dinh Nguyen <dinh.nguyen@linux.intel.com>
> ---
> v2: add platform specific platforms to DTS files
> ---
>  .../boot/dts/altera/socfpga_stratix10.dtsi    |  4 ++
>  .../dts/altera/socfpga_stratix10_socdk.dts    | 31 +++++++++
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  4 ++
>  .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
>  .../boot/dts/intel/socfpga_agilex_socdk.dts   | 66 +++++++++++++++++++
>  .../dts/intel/socfpga_agilex_socdk_nand.dts   | 66 +++++++++++++++++++
>  .../boot/dts/intel/socfpga_n5x_socdk.dts      | 47 +++++++++++++
>  7 files changed, 284 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 41c9eb51d0ee..2526afa687d6 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -633,6 +633,10 @@ svc {
>  				fpga_mgr: fpga-mgr {
>  					compatible = "intel,stratix10-soc-fpga-mgr";
>  				};
> +
> +				hwmon: temp-volt {

Node names should be generic, so maybe just hwmon.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +					compatible = "intel,socfpga-stratix10-hwmon", "intel,socfpga-hwmon";

Test your bindings. Your bindings or this part do not match at all.
Driver does not match it either.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 41c9eb51d0ee..2526afa687d6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -633,6 +633,10 @@  svc {
 				fpga_mgr: fpga-mgr {
 					compatible = "intel,stratix10-soc-fpga-mgr";
 				};
+
+				hwmon: temp-volt {
+					compatible = "intel,socfpga-stratix10-hwmon", "intel,socfpga-hwmon";
+				};
 			};
 		};
 	};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 38ae674f2f02..d506dcf8dc7c 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -212,3 +212,34 @@  qspi_rootfs: partition@3FE0000 {
 		};
 	};
 };
+
+&hwmon {
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VCC";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "1.0V VCCIO";
+			reg = <3>;
+		};
+
+		input@6 {
+			label = "0.9V VCCERAM";
+			reg = <6>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index f9674cc46764..552f9a05d039 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -666,6 +666,10 @@  svc {
 				fpga_mgr: fpga-mgr {
 					compatible = "intel,agilex-soc-fpga-mgr";
 				};
+
+				hwmon: temp-volt {
+					compatible = "intel,socfpga-agilex-hwmon", "intel,socfpga-hwmon";
+				};
 			};
 		};
 	};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index 6231a69204b1..c0642353b506 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -64,3 +64,69 @@  &watchdog0 {
 &fpga_mgr {
 	status = "disabled";
 };
+
+&hwmon {
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VCC";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "1.8V VCCIO_SDM";
+			reg = <3>;
+		};
+
+		input@4 {
+			label = "1.8V VCCPT";
+			reg = <4>;
+		};
+
+		input@5 {
+			label = "1.2V VCCCRCORE";
+			reg = <5>;
+		};
+
+		input@6 {
+			label = "0.9V VCCH";
+			reg = <6>;
+		};
+
+		input@7 {
+			label = "0.8V VCCL";
+			reg = <7>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+
+		input@10000 {
+			label = "Main Die corner bottom left max";
+			reg = <0x10000>;
+		};
+
+		input@20000 {
+			label = "Main Die corner top left max";
+			reg = <0x20000>;
+		};
+
+		input@30000 {
+			label = "Main Die corner bottom right max";
+			reg = <0x30000>;
+		};
+
+		input@40000 {
+			label = "Main Die corner top right max";
+			reg = <0x40000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 07c3f8876613..4bd8cdd8a7ca 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -138,3 +138,69 @@  qspi_rootfs: partition@3FE0000 {
 		};
 	};
 };
+
+&hwmon {
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VCC";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "1.8V VCCIO_SDM";
+			reg = <3>;
+		};
+
+		input@4 {
+			label = "1.8V VCCPT";
+			reg = <4>;
+		};
+
+		input@5 {
+			label = "1.2V VCCCRCORE";
+			reg = <5>;
+		};
+
+		input@6 {
+			label = "0.9V VCCH";
+			reg = <6>;
+		};
+
+		input@7 {
+			label = "0.8V VCCL";
+			reg = <7>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+
+		input@10000 {
+			label = "Main Die corner bottom left max";
+			reg = <0x10000>;
+		};
+
+		input@20000 {
+			label = "Main Die corner top left max";
+			reg = <0x20000>;
+		};
+
+		input@30000 {
+			label = "Main Die corner bottom right max";
+			reg = <0x30000>;
+		};
+
+		input@40000 {
+			label = "Main Die corner top right max";
+			reg = <0x40000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 51f83f96ec65..bfee1ca0bd6e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -114,3 +114,69 @@  &usb0 {
 &watchdog0 {
 	status = "okay";
 };
+
+&hwmon {
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VCC";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "1.8V VCCIO_SDM";
+			reg = <3>;
+		};
+
+		input@4 {
+			label = "1.8V VCCPT";
+			reg = <4>;
+		};
+
+		input@5 {
+			label = "1.2V VCCCRCORE";
+			reg = <5>;
+		};
+
+		input@6 {
+			label = "0.9V VCCH";
+			reg = <6>;
+		};
+
+		input@7 {
+			label = "0.8V VCCL";
+			reg = <7>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+
+		input@10000 {
+			label = "Main Die corner bottom left max";
+			reg = <0x10000>;
+		};
+
+		input@20000 {
+			label = "Main Die corner top left max";
+			reg = <0x20000>;
+		};
+
+		input@30000 {
+			label = "Main Die corner bottom right max";
+			reg = <0x30000>;
+		};
+
+		input@40000 {
+			label = "Main Die corner top right max";
+			reg = <0x40000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 08c088571270..090b0382db98 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -129,3 +129,50 @@  &usb0 {
 &watchdog0 {
 	status = "okay";
 };
+
+&hwmon {
+	compatible = "intel,socfpga-n5x-hwmon", "intel,socfpga-hwmon";
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VDD";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "0.8V VDD_SDM";
+			reg = <3>;
+		};
+
+		input@4 {
+			label = "1.8V VCCADC";
+			reg = <4>;
+		};
+
+		input@5 {
+			label = "1.8V VCCPD";
+			reg = <5>;
+		};
+
+		input@6 {
+			label = "1.8V VCCIO_SDM";
+			reg = <6>;
+		};
+
+		input@7 {
+			label = "0.8V VDD_HPS";
+			reg = <7>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+	};
+};