| Message ID | 20230907052639.16491-3-W_Armin@gmx.de (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | hwmon: (sch5627) Make limit registers writable | expand |
On Thu, Sep 07, 2023 at 07:26:36AM +0200, Armin Wolf wrote: > When the lock bit inside SCH5627_REG_CTRL is set, then the virtual > registers become read-only until the next power cycle. > Disallow write access to those registers in such a case. > > Tested on a Fujitsu Esprimo P720. > > Fixes: aa9f833dfc12 ("hwmon: (sch5627) Add pwmX_auto_channels_temp support") > Signed-off-by: Armin Wolf <W_Armin@gmx.de> Applied. Thanks, Guenter
diff --git a/drivers/hwmon/sch5627.c b/drivers/hwmon/sch5627.c index 0eefb8c0aef2..bf408e35e2c3 100644 --- a/drivers/hwmon/sch5627.c +++ b/drivers/hwmon/sch5627.c @@ -34,6 +34,7 @@ #define SCH5627_REG_CTRL 0x40 #define SCH5627_CTRL_START BIT(0) +#define SCH5627_CTRL_LOCK BIT(1) #define SCH5627_CTRL_VBAT BIT(4) #define SCH5627_NO_TEMPS 8 @@ -231,6 +232,14 @@ static int reg_to_rpm(u16 reg) static umode_t sch5627_is_visible(const void *drvdata, enum hwmon_sensor_types type, u32 attr, int channel) { + const struct sch5627_data *data = drvdata; + + /* Once the lock bit is set, the virtual registers become read-only + * until the next power cycle. + */ + if (data->control & SCH5627_CTRL_LOCK) + return 0444; + if (type == hwmon_pwm && attr == hwmon_pwm_auto_channels_temp) return 0644;
When the lock bit inside SCH5627_REG_CTRL is set, then the virtual registers become read-only until the next power cycle. Disallow write access to those registers in such a case. Tested on a Fujitsu Esprimo P720. Fixes: aa9f833dfc12 ("hwmon: (sch5627) Add pwmX_auto_channels_temp support") Signed-off-by: Armin Wolf <W_Armin@gmx.de> --- drivers/hwmon/sch5627.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.39.2