| Message ID | 20240603-apol-ina2xx-fix-v3-2-b9eff3158e4e@axis.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | hwmon: (ina2xx):Add Suppor for passing alert polarity from device tree to driver | expand |
On 6/3/24 03:08, Amna Waseem wrote: > The INA230 has an Alert pin which is asserted when the alert > function selected in the Mask/Enable register exceeds the > value programmed into the Alert Limit register. Assertion is based > on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable register). > It is default set to value 0 i.e Normal (active-low open collector). > However, hardware can be designed in such a way that expects Alert pin > to become active high if a user-defined threshold in Alert limit > register has been exceeded. This patch adds a way to pass alert polarity > value to the driver via device tree. > > Signed-off-by: Amna Waseem <Amna.Waseem@axis.com> > --- > drivers/hwmon/ina2xx.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c > index d8415d1f21fc..101346d26c88 100644 > --- a/drivers/hwmon/ina2xx.c > +++ b/drivers/hwmon/ina2xx.c > @@ -73,6 +73,11 @@ > #define INA226_READ_AVG(reg) (((reg) & INA226_AVG_RD_MASK) >> 9) > #define INA226_SHIFT_AVG(val) ((val) << 9) > > +#define INA226_ALERT_POLARITY_MASK 0x0002 > +#define INA226_SHIFT_ALERT_POLARITY(val) ((val) << 1) > +#define INA226_ALERT_POL_LOW 0 > +#define INA226_ALERT_POL_HIGH 1 > + > /* bit number of alert functions in Mask/Enable Register */ > #define INA226_SHUNT_OVER_VOLTAGE_BIT 15 > #define INA226_SHUNT_UNDER_VOLTAGE_BIT 14 > @@ -178,6 +183,17 @@ static u16 ina226_interval_to_reg(int interval) > return INA226_SHIFT_AVG(avg_bits); > } > > +static int ina2xx_set_alert_polarity(struct ina2xx_data *data, > + unsigned long val) > +{ > + if (!(val == 0 || val == 1)) > + return -EINVAL; > + The above check is completely unnecessary. This is a static function, and the parameters are known to be either INA226_ALERT_POL_LOW or INA226_ALERT_POL_HIGH. Guenter
diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index d8415d1f21fc..101346d26c88 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -73,6 +73,11 @@ #define INA226_READ_AVG(reg) (((reg) & INA226_AVG_RD_MASK) >> 9) #define INA226_SHIFT_AVG(val) ((val) << 9) +#define INA226_ALERT_POLARITY_MASK 0x0002 +#define INA226_SHIFT_ALERT_POLARITY(val) ((val) << 1) +#define INA226_ALERT_POL_LOW 0 +#define INA226_ALERT_POL_HIGH 1 + /* bit number of alert functions in Mask/Enable Register */ #define INA226_SHUNT_OVER_VOLTAGE_BIT 15 #define INA226_SHUNT_UNDER_VOLTAGE_BIT 14 @@ -178,6 +183,17 @@ static u16 ina226_interval_to_reg(int interval) return INA226_SHIFT_AVG(avg_bits); } +static int ina2xx_set_alert_polarity(struct ina2xx_data *data, + unsigned long val) +{ + if (!(val == 0 || val == 1)) + return -EINVAL; + + return regmap_update_bits(data->regmap, INA226_MASK_ENABLE, + INA226_ALERT_POLARITY_MASK, + INA226_SHIFT_ALERT_POLARITY(val)); +} + /* * Calibration register is set to the best value, which eliminates * truncation errors on calculating current register in hardware. @@ -659,6 +675,25 @@ static int ina2xx_probe(struct i2c_client *client) if (ret) return dev_err_probe(dev, ret, "failed to enable vs regulator\n"); + if (chip == ina226) { + if (of_property_read_bool(dev->of_node, "ti,alert-polarity-active-high")) { + ret = ina2xx_set_alert_polarity(data, + INA226_ALERT_POL_HIGH); + if (ret < 0) { + return dev_err_probe(dev, ret, + "failed to set alert polarity active high\n"); + } + } else { + /* Set default value i.e active low */ + ret = ina2xx_set_alert_polarity(data, + INA226_ALERT_POL_LOW); + if (ret < 0) { + return dev_err_probe(dev, ret, + "failed to set alert polarity active low\n"); + } + } + } + ret = ina2xx_init(data); if (ret < 0) { dev_err(dev, "error configuring the device: %d\n", ret);
The INA230 has an Alert pin which is asserted when the alert function selected in the Mask/Enable register exceeds the value programmed into the Alert Limit register. Assertion is based on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable register). It is default set to value 0 i.e Normal (active-low open collector). However, hardware can be designed in such a way that expects Alert pin to become active high if a user-defined threshold in Alert limit register has been exceeded. This patch adds a way to pass alert polarity value to the driver via device tree. Signed-off-by: Amna Waseem <Amna.Waseem@axis.com> --- drivers/hwmon/ina2xx.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)