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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:09:07.3658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94d0beb2-0550-4140-7982-08dcd2f9cb11 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4167 - Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a syncronysation method. By defining, a register access path, we use APML modules and library for all APML transactions. Without having to use external tools such as i2c-tools, which may cause race conditions. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v2: - Add ioctl description comment Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 22 ++++++++++++++++++++++ include/uapi/misc/amd-apml.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 0ec7fcd1f73e..7907524909e2 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -351,6 +351,24 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, return ret; } +static int rmi_register_xfer(struct sbrmi_data *data, + struct apml_message *msg) +{ + int ret; + + mutex_lock(&data->lock); + if (msg->data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) + ret = regmap_read(data->regmap, + msg->data_in.reg_in[AMD_SBI_REG_OFF_INDEX], + &msg->data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX]); + else + ret = regmap_write(data->regmap, + msg->data_in.reg_in[AMD_SBI_REG_OFF_INDEX], + msg->data_in.reg_in[AMD_SBI_REG_VAL_INDEX]); + mutex_unlock(&data->lock); + return ret; +} + static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) { int __user *arguser = (int __user *)arg; @@ -384,6 +402,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) /* MCAMSR protocol */ ret = rmi_mca_msr_read(data, &msg); break; + case APML_REG: + /* REG R/W */ + ret = rmi_register_xfer(data, &msg); + break; default: pr_err("Command:0x%x not recognized\n", msg.cmd); break; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index f26b83b933de..ea8ebff495bf 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -10,6 +10,7 @@ enum apml_protocol { APML_CPUID = 0x1000, APML_MCA_MSR, + APML_REG, }; /* These are byte indexes into data_in and data_out arrays */ @@ -28,6 +29,7 @@ struct apml_message { * Mailbox Messages: 0x0 ... 0x999 * APML_CPUID: 0x1000 * APML_MCA_MSR: 0x1001 + * APML_REG: 0x1002 */ __u32 cmd; @@ -45,6 +47,7 @@ struct apml_message { /* * [0]...[3] mailbox 32bit input * cpuid & mca msr, + * rmi rd/wr: reg_offset * [4][5] cpuid & mca msr: thread * [4] rmi reg wr: value * [6] cpuid: ext function & read eax/ebx or ecx/edx @@ -85,6 +88,7 @@ struct apml_message { * - Mailbox message read/write(0x0~0x999) * - CPUID read(0x1000) * - MCAMSR read(0x1001) + * - Register read/write(0x1002) * - returning "-EFAULT" if none of the above * "-EPROTOTYPE" error is returned to provide additional error details */